Arm Limited

A method of operating a graphics processor when performing a certain sequence of rendering jobs that produces a series of progressively lower resolution versions of the same render output comprising issuing rendering tasks for different rendering jobs concurrently and controlling processing for a later rendering job using a respective ‘task completion status’ data structure associated with the earlier rendering job on which it depends, wherein the looking up of respective entries in the ‘task completion status’ data structure takes into account the change in resolution between the first, earlier rendering job and the second, later rendering job.

A method to debug instruction execution errors in a simulated computer system is provided. The method includes generating two separate simulations of the same system and causing a code including a set of instructions to execute on the two separate simulations. The computer implemented method further includes performing an efficient trace operation starting from a start instruction to an end instruction of the set of instructions on the two separate simulations. When trace operation is performed, an instruction execution deviation is identified between the code executed in the two separate simulations by comparing checksum values at a reporting frequency, determining that the comparison of the checksum values indicates a mismatch, and using instruction count and the reporting frequency to capture at least one instruction leading up to the instruction execution deviation.

A graphics processing system includes a graphics processor that executes a tile-based graphics processing pipeline. The graphics processing pipeline comprises a sequence of one or more geometry processing stages to perform geometry processing, a binning stage that generates data structures for identifying geometry to be processed for respective rendering tiles of a render output being generated, and a rendering stage for rendering tiles of a render output being generated. Some of the geometry processing of the graphics processing pipeline being executed can be deferred until the rendering stage. It is determined whether previously deferred geometry processing for a render output should no longer be deferred until the rendering stage, and, if so, an indication that previously deferred geometry processing should no longer be deferred until the rendering stage is provided to the graphics processor. The graphics processor then performs previously deferred geometry processing in response to the indication.

A graphics processor that executes a tile-based graphics processing pipeline. The graphics processing pipeline comprises a sequence of one or more geometry processing stages to perform geometry processing, a binning stage that generates data structures for identifying geometry to be processed for respective rendering tiles of a render output being generated, and a rendering stage for rendering tiles of a render output being generated. Some of the geometry processing of the graphics processing pipeline being executed can be deferred until the rendering stage. When generating a render output an amount of geometry processing to be performed at the rendering stage is tracked for each region of a plurality of regions that the render output has been divided into, and when the amount of geometry processing to be performed at the rendering stage for a region reaches a threshold value, the rendering of geometry for the region is triggered.

An apparatus, comprises granule protection checking circuitry to obtain granule protection information associated with a target granule of physical addresses comprising a target physical address, and determine, based on the granule protection information, whether a selected physical address space associated with the target physical address is permitted to access the target granule of physical addresses. The apparatus comprises prefetch circuitry configured to initiate a prefetch operation for the target physical address enabling target data identified by the target physical address to be prefetched into a cache in advance of the granule protection checking circuitry determining whether the selected physical address space is permitted to access the target granule of physical addresses.

A direct memory access controller (DMAC) includes virtual channels, physical channels and a context manager. A virtual channel is configured to generate a flow control signal for execution of a direct memory access (DMA) command. A physical channel includes read and write control logic to initiate, responsive to the flow control signal, transfer of data from source device to a destination device in accordance with the DMA command. The context manager includes allocation logic configured to arbitrate between allocation requests from the virtual channels and allocate a physical channel to a selected virtual channel and routing logic configured to route a flow control signal from the selected virtual channel to the allocated physical channel and to route a status signal between the allocated physical channel and the selected virtual channel.

Methods of context switching, and corresponding computer programs, storage media, and apparatuses are disclosed. Data processing operations are performed in a first context and a routine is called which is to be executed in a second context. Initially the routine executes in the first context. Then memory region definitions other than those required for execution of the routine are disabled. A temporary switch is made to a set of all-cacheable memory access attributes. Then memory region definitions required for execution of the routine are copied into one or more spare elements of a memory region definitions register. An atomic switch of execution of the routine to a temporary context using a temporary memory map is carried out, by enabling the copy of the one or more memory region definitions required for execution of the routine and disabling the original versions. Then a second memory map is set up by storing a second set of memory region definitions in one or more predetermined elements of the memory region definitions register. Finally another atomic switch is carried out, switching execution of the routine to the second context using the second memory map by enabling new second set of memory region definitions and disabling the temporary copies of the memory region definitions.

Various implementations described herein refer to a device having a cell structure with multiple transistors including active n-type transistors and active p-type transistors disposed together within a cell boundary. The active n-type transistors may have a first diffusion region formed within the cell boundary at a first end of the cell structure. The active p-type transistors may have a second diffusion region formed within the cell boundary at a second end of the cell structure. The active p-type transistors may have a vacated region cut-out from the second diffusion region, and/or the active n-type transistors may have a vacated region cut-out from the first diffusion region.

An apparatus has bridge circuitry to communicate transport packets between a transport network and data processing circuitry. Some or all of the data processing circuitry operates in a given reset domain other than the reset domain of the transport network. The apparatus also has packet tracking circuitry to monitor the transport packets received at the bridge circuitry and to track whether any required responses have been provided. The reset handling circuitry is responsive to a reset request for the given reset domain to: cause the bridge circuitry to reject new transport packets received for the domain; and when the packet tracking circuitry indicates that all required responses have been provided, accept the reset request for the given reset domain and allow the data processing circuitry to carry out a reset for the data processing circuitry operating in the given reset domain.

A true random number generator (TRNG) as described herein can include a ring oscillator; and a sampling circuit coupled to an intermediate node of the ring oscillator, wherein the sampling circuit includes a reset, wherein the ring oscillator and the sampling circuit are formed of components from a standard cell library. The sampling circuit includes a storage cell selected for having a shortest oscillation period of a data input of the storage cell that results in a non-constant output. The reset of the sampling circuit can include a logic gate or be built-in reset functionality of the storage cell.