Company patents
ATOMERA INCORPORATED
ATOMERA INCORPORATED demonstrates a dynamic patent strategy, with a surprising recent emergence in Photovoltaic / Photoconductive Devices, where all 6 patents (4.7% of its portfolio) were filed so far in 2026, indicating a new strategic direction. This contrasts with a significant shift away from its historically dominant Transistor & Device Structure category, which saw a sharp decline of -64.5% in 2025 and -100.0% so far in 2026, despite representing 44.9% of its total portfolio.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
127 US filings (since 2023) · 9 categories · 20 themes
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Focuses on advanced pixel architectures, often involving vertical stacking (3D) or silicon-on-insulator (SOI) structures, to improve performance, density, or functionality of photodiodes, transistors, and floating diffusion regions within image sensor pixels.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Focuses on novel semiconductor materials, heterostructures, and doping profiles to improve photovoltaic conversion efficiency, stability, and spectral response.
The design and manufacturing of integrated circuits that combine optical and electronic components, particularly for high-speed data communication between processors and memory.
Image sensors tailored for specific advanced functionalities beyond basic image capture, such as high dynamic range (HDR) imaging, single-photon detection, auto-focus, or distance measurement (LiDAR), often incorporating specialized pixel designs or processing.
Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Devices utilizing piezoelectric materials to generate and filter acoustic waves, often for radio frequency applications, including surface acoustic wave (SAW) and bulk acoustic wave (BAW) structures.
Patents
Showing 71-80 of 118
Semiconductor Device Manufacturing Processes