Low latency, error relative, Reed-Solomon decoder

[0001]This application claims priority to U.S. Provisional Patent Application No. 63/494,062, filed Apr. 4, 2023, the contents of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

[0002]The present disclosure relates to efficiency enhancements for a Reed-Solomon decoder.

BACKGROUND

[0003]Communication over the Internet, and particularly the world wide web, is constantly growing, and with it so is the demand for ever faster and reliable connections. One component that imposes a constant delay on traffic passing through certain endpoints of a data communication network, such as one based on Ethernet or InfiniBand, is the Reed-Solomon Forward Error Correction (RS-FEC) decoder. The RS-FEC decoder is configured to correct bit errors that occur in high bandwidth (e.g., 100G, 200G, 400G, and 800G) links that use, e.g., PAM4 modulation and/or NRZ modulation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 shows a network having a plurality of endpoints that may be in communication with one another via a network, and where reduced calculation FEC decoder logic is hosted by at least one receiver of at least one of the endpoints, according to an example embodiment.

[0005]FIG. 2 shows a path of a message and its treatment through a Reed-Solomon FEC decoder including the reduced calculation FEC decoder logic, according to an example embodiment.

[0006]FIG. 3 shows a series of operations for executing forward error correction with reduced calculation FEC decoder logic, according to an example embodiment.

[0007]FIG. 4 is a block diagram of a computing device that may be configured to execute reduced calculation FEC decoder logic, and perform the techniques described herein, according to an example embodiment.

DETAILED DESCRIPTION

Overview

[0008]In one embodiment, a device is provided. The device includes an interface configured to enable network communications, a memory, and one or more processors coupled to the interface and the memory, and configured to: receive a message, process the message using forward error correction, in response to a predetermined condition, bypass at least some iterative calculations that are performed by the forward error correction, and output a processed message. The predetermined condition may be that all coefficients of a syndrome representative of the message are zero or that a degree of a value resulting from the iterative calculations is lower than a maximum number of errors correctable by the forward error correction. A latency resulting from the processing of the message using the forward error correction may be proportional to the number, e.g., the total number, of errors in the message.

[0009]In another embodiment, a method to operate forward error correction (FEC) is presented. The method may include receiving a message, processing the message using forward error correction, in response to a predetermined condition, bypassing at least some iterative calculations that are performed by the forward error correction, and outputting a processed message. The predetermined condition may be that all coefficients of a polynomial syndrome representative of the message are zero or that a degree of a value resulting from the iterative calculations is lower than a maximum number of errors correctable by the forward error correction.

EXAMPLE EMBODIMENTS

[0010]FIG. 1 shows a network 100 having a plurality of endpoints designated, e.g., as endpoint 150, endpoint 150(1), and endpoint 150(2) that may be in communication with one another via network 120, and where reduced calculation control logic 250 may be hosted by at least one receiver 200 of at least one of the endpoints, namely endpoint 150, according to an example embodiment. More specifically, and taking endpoint 150 as a representative example, receiver 200 may be an optical or electrical receiver with Forward Error Correction (FEC) 230 deployed therein. For example, receiver 200 may be part of an Ethernet Media Access Control (MAC) layer operating according to the IEEE 802.3 standard. As will be explained in more detail in connection with, e.g., FIG. 2, FEC 230 may be implemented as a Reed-Solomon FEC, or RS-FEC, along with reduced calculation control logic 250. In accordance with an embodiment, and as explained in detail below, FEC 230 is enhanced with reduced calculation control logic 250 to operate in a more efficient manner by detecting whether a particular predetermined condition has occurred in connection with processing a given block of bits or message and, if so, prematurely terminating selected remaining compute operations for that given block of bits or message.

[0011]An RS-FEC decoder is a systematic block code decoder that protects a constant number of bits (i.e., a message or part of a message) by adding redundant information to a block of bits. The added redundant information is referred to as “parity.” In operation, and in one possible embodiment, the RS-FEC decoder operates by first calculating a block syndrome polynomial using an entire received block, including the parity information. The next step takes the syndrome polynomial and resolves an error location polynomial and a magnitude polynomial from which the locations and values of the errors can be extracted.

[0012]Calculating the location and magnitude polynomials is a significant function of the decoder and involves a massive calculation, which is performed in what is often referred to as a “key equation solver.” The massive calculation consumes power and adds latency regardless of the number of errors in the block and is designed to match the FEC block throughput even when encountering the maximal number of errors that can be corrected.

[0013]Interestingly, a probability distribution of the number of errors in FEC blocks shows that the vast majority of the blocks have no errors at all, or perhaps only a single error. Moreover, the probability for more errors in a FEC block drops exponentially with the number of errors.

[0014]These findings lead to the conclusion that, for much of the time, the massive calculation performed by the key equation solver in an FEC decoder is of limited value. The methodology described herein exploits these findings and operates to reduce such computing activities. Beneficially, shortening the instances of the calculation can lead to significant improvements in power and in average latency.

[0015]In this regard, and as will be explained in detail below, the embodiments described herein take advantage of a given link's characteristics and introduce an FEC decoder whose latency and power consumption are proportional to, or dependent on, the number of errors. Consequently, most of the time, data throughput experiences minimal latency and power is saved.

[0016]It is noted that while many Reed-Solomon decoders implementations exist, most are based on an algorithm called “Berlekamp-Massey.” One issue with Berlekamp-Massey, and similar methods, is that they take a long time to correct each message, regardless of the number of errors in the message.

[0017]More specifically, the latency of implementations of such algorithms is on the order of 3*(Maximum number of errors)+1 clock cycles and, in theory, it may be possible to have an implementation that has a latency on the order of 2*(Maximum number of errors)+1 clock cycles. Taking RS-FEC (544,514) code as an example, the maximal number of correctable errors is 15. Accordingly, the latency is 46 clock cycles or 31 clock cycles, for the normal and fastest theoretical implementations, respectively.

[0018]Notably, approaches like Berlekamp-Massey take the same amount of time to fix one error as they do to fix many errors. This effectively means that such approaches treat each message as if it were a worst-case scenario.

[0019]Unlike other approaches, including those that employ “Euclid's algorithm” in the key equation solver, the embodiments described herein provide an approach in which the degree of latency is relative to the number of errors that need to be fixed.

[0020]The embodiments may be based on two independent mechanisms:

[0021]First, the massive calculation is bypassed or prematurely terminated when all coefficients of a syndrome polynomial are 0. That is, when all coefficients of the syndrome are 0, it means that there are no errors in the FEC block, and thus performing the massive calculation provides no benefit.

[0022]Second, the iterative loop of calculations (e.g., in some cases polynomial division, or other iterative calculations on, e.g., variables, coefficients, arrays, symbols, or strings of bits) is stopped or prematurely terminated when reaching the point in which the degree of, e.g., a residue polynomial (or other selected polynomial or value) is lower than a maximum number of errors. This iterative process or calculation may be used to calculate the polynomials that represent the location of the errors and their value. Once the error magnitude polynomial's degree is lower than the maximum possible number of errors it means that no more errors will be found for this FEC block.

[0023]The first mechanism is effective when there are no errors, while the second mechanism is effective whenever the number of actual errors is smaller than the maximal number of errors.

[0024]In other words, predetermined conditions for bypassing or prematurely ending or terminating iterative calculations in the key equation solver may include that (1) all coefficients of the syndrome polynomial are zero or (2) the degree (order or rank) of a polynomial resulting from the iterative process or calculations is lower than a maximum number of errors.

[0025]A more rigorous explanation of the approach disclosed herein is provided below.

[0026]Error correction operates by sending a relatively large message along with a relatively small number of parity bits, which makes it possible to correct many errors that may have been added to the message along the communications pathway.

[0027]The Reed-Solomon method may be outlined in four steps as follows:

[0028]STEP 1: Read the message as if it were a polynomial. This means splitting the message into pieces of, e.g., 10 bits, called symbols, and considering each piece as a coefficient of a polynomial: M(x)=First10Bits·x^{MessageSize−1}+Second10Bits·x^{MessageSize−2}+ . . .

[0029]STEP 2: Concatenate the parity. Parity is chosen such that the entire message T(x) has exactly 2t known roots. As such, if the roots are denoted as α₁, α₂, . . . , α_2t, then T(α_i)=0. It is noted that t is equal to the maximum number of errors that can be corrected.

[0030]STEP 3: A message is sent, and errors are (typically inadvertently, but not unexpectedly) added to it during transmission. The errors are considered as polynomial

[0031]$E\left(x\right)={\sum }_{i=0}^{t-1}{E}_i·x^{e_i}={\sum }_{i=0}^{t-1}{\mathrm{errMagnitude}}_i·x^{{\mathrm{errLocation}}_i}.$

[0032]STEP 4: Decode. A message R(x)=T(x)+E(x) is received and an operation is performed to recreate T(x)=R(x)−E(x). For that, all that is needed to find is E(x). By plugging in the roots

[0033]$R\left({\alpha }_i\right)=T\left({\alpha }_i\right)+E\left({\alpha }_i\right)=E\left({\alpha }_i\right)={\sum }_{j=0}^{t-1}{E}_j·{\alpha }_i^{e_j}2t$
Key Equations are obtained with 2t missing variables which can be solved to find E(x).

[0034]Decoding may be explained as follows. Note that t=parity_size/2=maximum number of correctable errors, and v=number of actual errors. The key equation solver assumes v≤t.

[0035]T(x)—A polynomial representing the original message sent and the parity.

[0036]$E\left(x\right)={\sum }_{i=0}^{v-1}{E}_i·x^{e_i}={\sum }_{i=0}^{v-1}\mathrm{errror}·{\mathrm{magnitude}}_i·x^{\mathrm{error}·{\mathrm{location}}_i}-\mathrm{Errors}$
Errors added to the message.

[0037]R(x)=T(x)+E(x)—The message received.

[0038]Note: T(x) has 2t roots denoted by α⁰, α¹, . . . , α^2t−1 meaning ∇i∈{0,1, . . . ,2t−1}

[0039]$R\left({\alpha }^i\right)=T\left({\alpha }^i\right)+E\left({\alpha }^i\right)=E\left({\alpha }^i\right)$

[0040]S(x)=S₀+S₁x+ . . . +S_2t-1x^2t−1—The syndrome polynomial: S_i=R(αⁱ)=E(αⁱ).

[0041]The key equation solver uses the syndrome polynomial to solve these 2t equations by finding:

[0042]$\Lambda \left(x\right)={\prod }_{i=0}^{v-1}\left(1+{\alpha }^{e_i}x\right)-\mathrm{Error}$

[0043]Error location polynomial, whose roots are α^−ei=α^−err,loci.

[0044]$\Omega \left(x\right)=\left[S\left(x\right)·\Lambda \left(x\right)\right]\mathrm{mod}{x}^{2t}={\sum }_{i=0}^{v-1}{\Omega }_i{x}^i-\mathrm{Error}$

[0045]Error magnitude polynomial:

[0046]${\Omega }_i={\sum }_{j=0}^i{S}_j{\Lambda }_{i-j}.$

[0047]Note: Ω(x) is important because it helps to find the coefficients of

[0048]$E\left(x\right)={\sum }_{i=0}^{v-1}{E}_i·x^{e_i}:E_i={\alpha }^{e_i}·\Omega \left({\alpha }^{-e}\right)/{\Lambda }^{\prime }\left({\alpha }^{-e}\right)$

[0049]Solving the key equation—Euclid's method

[0050]The goal here is to use the calculated syndrome polynomial S(x) to find the error location Λ(x) and error magnitude Ω(x) polynomials. Euclid's method may be used.

[0051]Specifically, by definition, Ω(x)=[S(x)·Λ(x)]mod x^2t. This means that there exists a polynomial F(x) such that S(x)·Λ(x)=F(x)·x^2t+Ω(x).

[0052]Euclid's theory shows that the following algorithm holds:
Initialize: r₀=x^2t,r₁=S(x),λ₀=0,λ₁=1,f₀=1,f₁=0
for(i=1;degree(r_i)≥t;i=i+1)
q=quotient(r_i−1/r_i)
r_i+1=r_i−1−qr_i#This means that r_i+1=remainder(r_i−1/r_i).
λ_i+1=λ_i−1−qλ_i
f_i+1=f_i−1−qf_i
Ω(x)=r_i
Λ(x)=λ_i
F(x)=f_i

[0053]The degree of r_i gets smaller with each iteration, meaning the algorithm runs no more than t iterations. Moreover, when there are v<t errors, the degree will get smaller by more than 1 in some iterations resulting in the algorithm taking approximately v instead of t iterations.

[0054]Hence, the fewer errors there are, the less time it takes to finish this calculation.

[0055]It is noted that no solution implements the Euclid method directly. This is because large polynomial division cannot be implemented in a single clock cycle and would require a very large area. Due to this, no known implementation can take advantage of the reduced number of iterations that the theoretical solution offers. Instead, the division is avoided with many simpler and repetitive operations, losing the significant advantage that the mathematical method offers.

[0056]The embodiments disclosed herein leverage the theoretical mathematical principles, but recognize when the practical existing implementations reach this “early finish” state and then extract the correct solution at this point.

[0057]Reference is now made to FIG. 2, which shows a path of a message and its treatment through receiver 200 including a Reed-Solomon FEC decoder including reduced calculation control logic 250, according to an example embodiment. As shown at block 210, a message and parity are sent from a source. At block 215, the message travels through a network (e.g., network 120) with the risk of errors being added to bits in the message to create a flawed message 225. Flawed message 225 reaches, e.g., a router, such as endpoint 150 (FIG. 1). Within endpoint 150 is receiver 200 with FEC 230, which generates a corrected or processed message 238, which may then be supplied, e.g., to an internal router for packet handling, etc.

[0058]As further shown, FEC 230 receives a (potentially) flawed message 225, which is supplied to Syndrome calculator 231, which applies a manipulation to the received message to create 2*t key equations represented by the Syndrome polynomial. The (potentially) flawed message 225 is also supplied to a first in-first out (FIFO) memory 232 so that the original (potentially) flawed message 225 is available for later processing for error correction. An output of Syndrome calculator 231 is provided to key equation solver 240, which uses an algorithm, e.g., the modified version of the Euclid method discussed above, to find the error location and error magnitude polynomials from the Syndrome polynomial. The Error location polynomial is supplied to block 233, which finds the roots of the error location polynomial and calculates an error magnitude factor according to, e.g., the method disclosed by Chien. At the same time, the error magnitude polynomial is supplied to block 234, which uses the error magnitude polynomial to calculate the magnitude of each error according to, e.g., the method disclosed by Forney. Block 235 divides the error magnitudes by their factor, and outputs an error message 237, which is subtracted, in block 236, from flawed message 225 that is supplied by FIFO memory 232. The corrected or processed message 238 is thus output and supplied to, e.g., a downstream element for, e.g., packet handling. In the event no errors are in the message 225, the message 225 stored in FIFO memory 232 may be output without performing subtraction in block 236.

[0059]Key equation solver 240 comprises block 242 and reduced calculation control logic 250. A syndrome polynomial generated by Syndrome calculator 231 is supplied to block 242, which iteratively performs part of the polynomial calculation (e.g., Euclid's method) (or other iterative calculation) at each clock cycle. An output of block 242 is supplied to reduced calculation control logic 250, which recognizes when no more iterations are required, and accordingly generates a stop or terminate command to block 242 and performs modifications to extract the correct solution from the current state. The current state is fed back to block 242 for successive iterative (polynomial) calculations.

[0060]As noted previously, two different mechanisms may be implemented by reduced calculation control logic 250 to “short circuit” a full number of (polynomial) calculation iterations by block 242.

[0061]The first mechanism operates to altogether bypass operations of the massive calculation when all coefficients of the syndrome polynomial are 0. When all coefficients of the syndrome polynomial are 0, it means that there are no errors in the FEC block being processed. In this regard, reduced calculation control logic 250 may monitor the inputted syndrome polynomial directly, as shown in the figure, and then operate to output the message 225 stored in FIFO memory 232.

[0062]The second mechanism operates to prematurely stop or terminate operation of the iterative loop of polynomial division (or other iterative calculation) that is implemented by block 242, when reaching the point in which the degree of the residue polynomial (or other polynomial or value) is lower than the maximum number of errors. This division process is used to calculate the polynomials that represent the location of the errors and their value. Once the residue's (or other value's) degree is lower than the maximum possible number of errors it means that no more errors will be found for the FEC block being processed. Reduced calculation control logic 250 monitors for this condition and sends an appropriate stop or terminate command to block 242, as appropriate.

[0063]Error correction in messages passing across, e.g., the Internet, is a vital part of any network device. This process consumes power, takes a long time to complete, and creates a constant delay in data transfer. The methodology described herein, by eliminating certain iterative calculations (e.g., polynomial division), may reduce average calculation efforts on the order of 90%, significantly reducing power consumption and latency of any network device that deploys the methodology.

[0064]FIG. 3 shows a series of operations for executing forward error correction with reduced calculation control logic 250, according to an example embodiment. At 310, an operation is configured to receive a message. At 312, an operation is configured to process the message using forward error correction. At 314, an operation is configured to, in response to a predetermined condition, bypass at least some iterative calculations that are performed by the forward error correction. And, at 316, an operation is configured to output a processed message.

[0065]FIG. 4 is a block diagram of a computing device that may be configured to execute forward error correction with reduced calculation control logic 250, and perform the techniques described herein, according to an example embodiment. In various embodiments, a computing device, such as computing device 400 or any combination of computing devices 400, may be configured as any entity/entities as discussed for the techniques depicted in connection with FIGS. 1-3 in order to perform operations of the various techniques discussed herein.

[0066]In at least one embodiment, the computing device 400 may include one or more processor(s) 402, one or more memory element(s) 404, storage 406, a bus 408, one or more network processor unit(s) 410 interconnected with one or more network input/output (I/O) interface(s) 412, one or more I/O interface(s) 414, and control logic 420 (which could include, for example, reduced calculation control logic 250. In various embodiments, instructions associated with logic for computing device 400 can overlap in any manner and are not limited to the specific allocation of instructions and/or operations described herein.

[0067]In at least one embodiment, processor(s) 402 is/are at least one hardware processor configured to execute various tasks, operations and/or functions for computing device 400 as described herein according to software and/or instructions configured for computing device 400. Processor(s) 402 (e.g., a hardware processor) can execute any type of instructions associated with data to achieve the operations detailed herein. In one example, processor(s) 402 can transform an element or an article (e.g., data, information) from one state or thing to another state or thing. Any of potential processing elements, microprocessors, digital signal processor, baseband signal processor, modem, PHY, controllers, systems, managers, logic, and/or machines described herein can be construed as being encompassed within the broad term ‘processor’.

[0068]In at least one embodiment, memory element(s) 404 and/or storage 406 is/are configured to store data, information, software, and/or instructions associated with computing device 400, and/or logic configured for memory element(s) 404 and/or storage 406. For example, any logic described herein (e.g., control logic 420) can, in various embodiments, be stored for computing device 400 using any combination of memory element(s) 404 and/or storage 406. Note that in some embodiments, storage 406 can be consolidated with memory element(s) 404 (or vice versa) or can overlap/exist in any other suitable manner.

[0069]In at least one embodiment, bus 408 can be configured as an interface that enables one or more elements of computing device 400 to communicate in order to exchange information and/or data. Bus 408 can be implemented with any architecture designed for passing control, data and/or information between processors, memory elements/storage, peripheral devices, and/or any other hardware and/or software components that may be configured for computing device 400. In at least one embodiment, bus 408 may be implemented as a fast kernel-hosted interconnect, potentially using shared memory between processes (e.g., logic), which can enable efficient communication paths between the processes.

[0070]In various embodiments, network processor unit(s) 410 may enable communication between computing device 400 and other systems, entities, etc., via network I/O interface(s) 412 (wired and/or wireless) to facilitate operations discussed for various embodiments described herein. In various embodiments, network processor unit(s) 410 can be configured as a combination of hardware and/or software, such as one or more Ethernet driver(s) and/or controller(s) or interface cards, Fibre Channel (e.g., optical) driver(s) and/or controller(s), wireless receivers/transmitters/transceivers, baseband processor(s)/modem(s), and/or other similar network interface driver(s) and/or controller(s) now known or hereafter developed to enable communications between computing device 400 and other systems, entities, etc. to facilitate operations for various embodiments described herein. In various embodiments, network I/O interface(s) 412 can be configured as one or more Ethernet port(s), Fibre Channel ports, any other I/O port(s), and/or antenna(s)/antenna array(s) now known or hereafter developed. Thus, the network processor unit(s) 410 and/or network I/O interface(s) 412 may include suitable interfaces for receiving, transmitting, and/or otherwise communicating data and/or information in a network environment.

[0071]I/O interface(s) 414 allow for input and output of data and/or information with other entities that may be connected to computing device 400. For example, I/O interface(s) 414 may provide a connection to external devices such as a keyboard, keypad, a touch screen, and/or any other suitable input and/or output device now known or hereafter developed. In some instances, external devices can also include portable computer readable (non-transitory) storage media such as database systems, thumb drives, portable optical or magnetic disks, and memory cards. In still some instances, external devices can be a mechanism to display data to a user, such as, for example, a computer monitor, a display screen, or the like.

[0072]In various embodiments, control logic 420 can include instructions that, when executed, cause processor(s) 402 to perform operations, which can include, but not be limited to, providing overall control operations of computing device; interacting with other entities, systems, etc. described herein; maintaining and/or interacting with stored data, information, parameters, etc. (e.g., memory element(s), storage, data structures, databases, tables, etc.); combinations thereof; and/or the like to facilitate various operations for embodiments described herein.

[0073]The programs described herein (e.g., control logic 420) may be identified based upon application(s) for which they are implemented in a specific embodiment. However, it should be appreciated that any particular program nomenclature herein is used merely for convenience; thus, embodiments herein should not be limited to use(s) solely described in any specific application(s) identified and/or implied by such nomenclature.

[0074]In various embodiments, entities as described herein may store data/information in any suitable volatile and/or non-volatile memory item (e.g., magnetic hard disk drive, solid state hard drive, semiconductor storage device, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), application specific integrated circuit (ASIC), etc.), software, logic (fixed logic, hardware logic, programmable logic, analog logic, digital logic), hardware, and/or in any other suitable component, device, element, and/or object as may be appropriate. Any of the memory items discussed herein should be construed as being encompassed within the broad term ‘memory element’. Data/information being tracked and/or sent to one or more entities as discussed herein could be provided in any database, table, register, list, cache, storage, and/or storage structure: all of which can be referenced at any suitable timeframe. Any such storage options may also be included within the broad term ‘memory element’ as used herein.

[0075]Note that in certain example implementations, operations as set forth herein may be implemented by logic encoded in one or more tangible media that is capable of storing instructions and/or digital information and may be inclusive of non-transitory tangible media and/or non-transitory computer readable storage media (e.g., embedded logic provided in: an ASIC, digital signal processing (DSP) instructions, software [potentially inclusive of object code and source code], etc.) for execution by one or more processor(s), and/or other similar machine, etc. Generally, memory element(s) 404 and/or storage 406 can store data, software, code, instructions (e.g., processor instructions), logic, parameters, combinations thereof, and/or the like used for operations described herein. This includes memory element(s) 404 and/or storage 406 being able to store data, software, code, instructions (e.g., processor instructions), logic, parameters, combinations thereof, or the like that are executed to carry out operations in accordance with teachings of the present disclosure.

[0076]In some instances, software of the present embodiments may be available via a non-transitory computer useable medium (e.g., magnetic or optical mediums, magneto-optic mediums, CD-ROM, DVD, memory devices, etc.) of a stationary or portable program product apparatus, downloadable file(s), file wrapper(s), object(s), package(s), container(s), and/or the like. In some instances, non-transitory computer readable storage media may also be removable. For example, a removable hard drive may be used for memory/storage in some implementations. Other examples may include optical and magnetic disks, thumb drives, and smart cards that can be inserted and/or otherwise connected to a computing device for transfer onto another computer readable storage medium.

Variations and Implementations

[0077]Embodiments described herein may include one or more networks, which can represent a series of points and/or network elements of interconnected communication paths for receiving and/or transmitting messages (e.g., packets of information) that propagate through the one or more networks. These network elements offer communicative interfaces that facilitate communications between the network elements. A network can include any number of hardware and/or software elements coupled to (and in communication with) each other through a communication medium. Such networks can include, but are not limited to, any local area network (LAN), virtual LAN (VLAN), wide area network (WAN) (e.g., the Internet), software defined WAN (SD-WAN), wireless local area (WLA) access network, wireless wide area (WWA) access network, metropolitan area network (MAN), Intranet, Extranet, virtual private network (VPN), Low Power Network (LPN), Low Power Wide Area Network (LPWAN), Machine to Machine (M2M) network, Internet of Things (IoT) network, Ethernet network/switching system, any other appropriate architecture and/or system that facilitates communications in a network environment, and/or any suitable combination thereof.

[0078]Networks through which communications propagate can use any suitable technologies for communications including wireless communications (e.g., 4G/5G/nG, IEEE 802.11 (e.g., Wi-Fi®/Wi-Fi6®), IEEE 802.16 (e.g., Worldwide Interoperability for Microwave Access (WiMAX)), Radio-Frequency Identification (RFID), Near Field Communication (NFC), Bluetooth™, mm.wave, Ultra-Wideband (UWB), etc.), and/or wired communications (e.g., T1 lines, T3 lines, digital subscriber lines (DSL), Ethernet, Fibre Channel, etc.). Generally, any suitable means of communications may be used such as electric, sound, light, infrared, and/or radio to facilitate communications through one or more networks in accordance with embodiments herein. Communications, interactions, operations, etc. as discussed for various embodiments described herein may be performed among entities that may directly or indirectly connected utilizing any algorithms, communication protocols, interfaces, etc. (proprietary and/or non-proprietary) that allow for the exchange of data and/or information.

[0079]Communications in a network environment can be referred to herein as ‘messages’, ‘messaging’, ‘signaling’, ‘data’, ‘content’, ‘objects’, ‘requests’, ‘queries’, ‘responses’, ‘replies’, etc. which may be inclusive of packets. As referred to herein and in the claims, the term ‘packet’ may be used in a generic sense to include packets, frames, segments, datagrams, and/or any other generic units that may be used to transmit communications in a network environment. Generally, a packet is a formatted unit of data that can contain control or routing information (e.g., source and destination address, source and destination port, etc.) and data, which is also sometimes referred to as a ‘payload’, ‘data payload’, and variations thereof. In some embodiments, control or routing information, management information, or the like can be included in packet fields, such as within header(s) and/or trailer(s) of packets. Internet Protocol (IP) addresses discussed herein and in the claims can include any IP version 4 (IPv4) and/or IP version 6 (IPv6) addresses.

[0080]To the extent that embodiments presented herein relate to the storage of data, the embodiments may employ any number of any conventional or other databases, data stores or storage structures (e.g., files, databases, data structures, data or other repositories, etc.) to store information.

[0081]Note that in this Specification, references to various features (e.g., elements, structures, nodes, modules, components, engines, logic, steps, operations, functions, characteristics, etc.) included in ‘one embodiment’, ‘example embodiment’, ‘an embodiment’, ‘another embodiment’, ‘certain embodiments’, ‘some embodiments’, ‘various embodiments’, ‘other embodiments’, ‘alternative embodiment’, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. Note also that a module, engine, client, controller, function, logic or the like as used herein in this Specification, can be inclusive of an executable file comprising instructions that can be understood and processed on a server, computer, processor, machine, compute node, combinations thereof, or the like and may further include library modules loaded during execution, object files, system files, hardware logic, software logic, or any other executable modules.

[0082]It is also noted that the operations and steps described with reference to the preceding figures illustrate only some of the possible scenarios that may be executed by one or more entities discussed herein. Some of these operations may be deleted or removed where appropriate, or these steps may be modified or changed considerably without departing from the scope of the presented concepts. In addition, the timing and sequence of these operations may be altered considerably and still achieve the results taught in this disclosure. The preceding operational flows have been offered for purposes of example and discussion. Substantial flexibility is provided by the embodiments in that any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings of the discussed concepts.

[0083]As used herein, unless expressly stated to the contrary, use of the phrase ‘at least one of’, ‘one or more of’, ‘and/or’, variations thereof, or the like are open-ended expressions that are both conjunctive and disjunctive in operation for any and all possible combination of the associated listed items. For example, each of the expressions ‘at least one of X, Y and Z’, ‘at least one of X, Y or Z’, ‘one or more of X, Y and Z’, ‘one or more of X, Y or Z’ and ‘X, Y and/or Z’ can mean any of the following: 1) X, but not Y and not Z; 2) Y, but not X and not Z; 3) Z, but not X and not Y; 4) X and Y, but not Z; 5) X and Z, but not Y; 6) Y and Z, but not X; or 7) X, Y, and Z.

[0084]Additionally, unless expressly stated to the contrary, the terms ‘first’, ‘second’, ‘third’, etc., are intended to distinguish the particular nouns they modify (e.g., element, condition, node, module, activity, operation, etc.). Unless expressly stated to the contrary, the use of these terms is not intended to indicate any type of order, rank, importance, temporal sequence, or hierarchy of the modified noun. For example, ‘first X’ and ‘second X’ are intended to designate two ‘X’ elements that are not necessarily limited by any order, rank, importance, temporal sequence, or hierarchy of the two elements. Further as referred to herein, ‘at least one of’ and ‘one or more of can be represented using the’ (s)′ nomenclature (e.g., one or more element(s)).

[0085]In sum, a device is provided. The device may include an interface configured to enable network communications, a memory, and one or more processors coupled to the interface and the memory, and configured to: receive a message, process the message using forward error correction, in response to a predetermined condition, bypass at least some iterative calculations that are performed by the forward error correction, and output a processed message, wherein a latency resulting from processing the message using the forward error correction is proportional to a number of errors in the message.

[0086]In the device, the forward error correction may be performed with a Reed-Solomon forward error correction decoder.

[0087]The one or more processors may be configured to bypass the at least some iterative calculations of a key equation solver of the Reed-Solomon forward error correction decoder.

[0088]In the device, the at least some iterative calculations comprise calculations according to Euclid's method.

[0089]In the device, the predetermined condition may be that all coefficients of a syndrome polynomial of the message are zero.

[0090]In the device, when the message contains no errors, the one or more processors may be configured to bypass all iterative calculations that are performed by the forward error correction.

[0091]In the device, the predetermined condition may be that a degree of a value resulting from at least one iterative calculation that is performed by the forward error correction is lower than a maximum number of errors correctable by the forward error correction, and the one or more processors may be configured to prematurely terminate an iterative calculation process when the degree of the value is lower than a maximum number of errors correctable by the forward error correction.

[0092]A method is also provided. The method may include receiving a message, processing the message using forward error correction, in response to a predetermined condition, bypassing at least some iterative calculations that are performed by the forward error correction, and outputting a processed message.

[0093]The method may further include performing the forward error correction with a Reed-Solomon forward error correction decoder.

[0094]The method may further include bypassing the at least some iterative calculations of a key equation solver of the Reed-Solomon forward error correction decoder.

[0095]In the method, the at least some iterative calculations may include calculations according to Euclid's method.

[0096]In the method, the predetermined condition may be that all coefficients of a syndrome polynomial that is representative of the message are zero.

[0097]In the method, the message may contain no errors.

[0098]The method may further include bypassing all iterative calculations that are performed by the forward error correction.

[0099]In the method, the predetermined condition may be that a degree of a value resulting from at least one iterative calculation that is performed by the forward error correction is lower than a maximum number of errors correctable by the forward error correction.

[0100]The method may further include prematurely terminating an iterative loop of calculations when the degree of the value is lower than a maximum number of errors correctable by the forward error correction.

[0101]In the method, a latency resulting from processing the message using forward error correction may be proportional to a number of errors in the message.

[0102]In still another embodiment, one or more non-transitory computer readable storage media encoded with instructions are provided that, when executed by a processor, cause the processor to: receive a message, process the message using forward error correction, in response to a predetermined condition, bypass at least some iterative calculations that are performed by the forward error correction, and output a processed message.

[0103]The instructions may be configured to cause the processor to bypass all iterative calculations that are performed by the forward error correction when the predetermined condition is that all coefficients of a syndrome polynomial that is representative of the message are zero.

[0104]The instructions may be configured to cause the processor to prematurely terminate an iterative loop of calculations when the predetermined condition is that a degree of a value is lower than a maximum number of errors correctable by the forward error correction.

[0105]Each example embodiment disclosed herein has been included to present one or more different features. However, all disclosed example embodiments are designed to work together as part of a single larger system or method. This disclosure explicitly envisions compound embodiments that combine multiple previously discussed features in different example embodiments into a single system or method.

[0106]One or more advantages described herein are not meant to suggest that any one of the embodiments described herein necessarily provides all of the described advantages or that all the embodiments of the present disclosure necessarily provide any one of the described advantages. Numerous other changes, substitutions, variations, alterations, and/or modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and/or modifications as falling within the scope of the appended claims.