US20260090289A1
APPARATUS AND PROCESS FOR MONOLITHIC STOCHASTIC COMPUTING ARCHITECTURE FOR ENERGY ARITHMETIC
Publication
Application
Classifications
IPC Classifications
CPC Classifications
Applicants
The Penn State Research Foundation
Inventors
Saptarshi Das, Harikrishnan Ravichandran, Yikai Zheng
Abstract
Embodiments relate to devices, circuits, and systems including s-bit generators constructed from memtransistors. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. The s-bit generator can be used to construct s-bit generator circuits that exploit the different sources of inherent stochasticity in 2D memtransistors (e.g., cycle-to-cycle fluctuations in the carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor, random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor, etc.) and combine it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits. Additional embodiments relate to integration of s-bit generators with 2D memtransistor based logic gates such as AND, MUX, XOR, and OR gates to perform arithmetic operations such as addition, subtraction, multiplication, and/or sorting.
Figures
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001]This patent application is related to and claims the benefit of priority to U.S. 63/408,285, filed on Sep. 20, 2022, the entire contents of which is incorporated by reference.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
[0002]This invention was made with government support under Grant No. W911NF-19-2-0338 awarded by the United States Army/ARO and under Grant No. DMR1539916 awarded by the National Science Foundation. The Government has certain rights in the invention.
FIELD OF THE INVENTION
[0003]Embodiments relate to s-bit generators constructed from memtransistors that exploit the different sources of inherent stochasticity in 2D memtransistors. The different sources of stochasticity can include cycle-to-cycle fluctuations in the carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor, random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor, etc., and combine it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits.
BACKGROUND OF THE INVENTION
[0004]The aggressive downscaling of feature sizes in silicon based complementary metal-oxide-semiconductor (CMOS) technology over the past five decades has led to an exponential growth in the computing power of modern-day computers. Today, computers can fly jets, control industrial processes, and solve optimization problems. In fact, computers can also beat professional players in the game of ‘Go’ and predict complex structures of proteins thanks to the remarkable progress in the field of artificial intelligence (AI). The ongoing revolution in AI is directly linked to the unfathomable data processing power by computers enabling implementation of deep learning and various other sophisticated machine learning algorithms. However, there is significant infrastructure cost associated with advanced AI and computing systems. For example, any mathematical algorithm implemented using hardware requires arithmetic operations such as addition, subtraction, multiplication, sorting, etc., which are executed using logic circuits consisting of hundreds of transistors that occupy large area and consume significant amount of energy. Furthermore, the von Neumann architecture necessitate frequent data shuttling between the arithmetic and the memory units to run algorithms adding area and energy overheads. Needless to say, these challenges are aggravated as the data size grows exponentially for both AI and no-AI platforms. Therefore, a new paradigm that can drastically reduce the area and energy cost of arithmetic operations can not only benefit cloud computing using supercomputers but also enable edge computing in resource-constrained internet of things (IoT) devices.
SUMMARY OF THE INVENTION
[0005]An exemplary embodiment relates to an s-bit generator configured to exploit inherent stochasticity in 2D memtransistors for stochastic bit (s-bit) generation.
[0006]An exemplary embodiment relates to an s-bit generator. The s-bit generator can include plural 2D memtransistors, an inverting amplifier, and a programmable threshold inverter. One or more s-bits can be generated from inherent stochasticity in the plural 2D memtransistors. In some embodiments, the plural 2D memtransistors form a voltage divider.
[0007]Inherent stochasticity in the plural 2D memtransistors can include one or more of: cycle-to-cycle fluctuations in carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor of the plural 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors, and/or random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors.
[0008]An exemplary embodiment relates to a s-bit generator. The s-bit generator includes plural memtransistors, comprising: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate; a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: MT3-drain, MT5-drain, and node N1. MT1-gate is connected to node N2. MT1-source is connected to: MT2-drain and MT4-gate via node N5. MT2-drain is connected to MT4-gate via node N5. MT2-gate is connected to node N3. MT2-source is connected to: MT4-source, MT6-source, and node N4. MT3-drain is connected to: MT1-drain, MT5-drain, and node N1. MT3-gate is connected to MT6-gate via node N6. MT3-source is connected to: MT6-gate via node N6 and MT4-drain via node N6. MT4-drain is connected to: MT3-source via node N6, MT3-gate via node N6, and MT6-gate via node N6. MT4-gate is connected to: MT1-source via node N5 and MT2-drain via node N5. MT4-source is connected to: MT2-source, MT6-source, and node N4. MT5-drain is connected to: MT1-drain, MT3-drain, and node N1. MT5-gate is connected to MT6-drain via node N7. MT6-drain is connected to: MT5-source via node N7 and MT5-gate via node N7. MT6-gate is connected to: MT3-source via node N6, MT3-gate via node N6, and MT4-drain via node N6. MT6-source is connected to: MT4-source, MT2-source, and node N4.
[0009]In some embodiments, the 2D channel is a monolayer.
[0010]In some embodiments, the monolayer includes MoS2.
[0011]An exemplary embodiment relates to a stochastic computing processor. The stochastic computing processor includes a processing module having a processor and a memory. The stochastic computing processor includes plural memtransistors, comprising: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate; a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: MT3-drain, MT5-drain, and node N1. MT1-gate is connected to node N2. MT1-source is connected to: MT2-drain and MT4-gate via node N5. MT2-drain is connected to MT4-gate via node N5. MT2-gate is connected to node N3. MT2-source is connected to: MT4-source, MT6-source, and node N4. MT3-drain is connected to: MT1-drain, MT5-drain, and node N1. MT3-gate is connected to MT6-gate via node N6. MT3-source is connected to: MT6-gate via node N6 and MT4-drain via node N6. MT4-drain is connected to: MT3-source via node N6, MT3-gate via node N6, and MT6-gate via node N6. MT4-gate is connected to: MT1-source via node N5 and MT2-drain via node N5. MT4-source is connected to: MT2-source, MT6-source, and node N4. MT5-drain is connected to: MT1-drain, MT3-drain, and node N1. MT5-gate is connected to MT6-drain via node N7. MT6-drain is connected to: MT5-source via node N7 and MT5-gate via node N7. MT6-gate is connected to: MT3-source via node N6, MT3-gate via node N6, and MT4-drain via node N6. MT6-source is connected to: MT4-source, MT2-source, and node N4.
[0012]In some embodiments, the stochastic computing processor has a non-von Neuman architecture.
[0013]An exemplary embodiment relates to a stochastic multiplier. The stochastic multiplier includes a first s-bit generator having plural memtransistors, comprising: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate; a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: MT3-drain, MT5-drain, and node N1. MT1-gate is connected to node N2. MT1-source is connected to: MT2-drain and MT4-gate via node N5. MT2-drain is connected to MT4-gate via node N5. MT2-gate is connected to node N3. MT2-source is connected to: MT4-source, MT6-source, and node N4. MT3-drain is connected to: MT1-drain, MT5-drain, and node N1. MT3-gate is connected to MT6-gate via node N6. MT3-source is connected to: MT6-gate via node N6 and MT4-drain via node N6. MT4-drain is connected to: MT3-source via node N6, MT3-gate via node N6, and MT6-gate via node N6. MT4-gate is connected to: MT1-source via node N5 and MT2-drain via node N5. MT4-source is connected to: MT2-source, MT6-source, and node N4. MT5-drain is connected to: MT1-drain, MT3-drain, and node N1. MT5-gate is connected to MT6-drain via node N7. MT6-drain is connected to: MT5-source via node N7 and MT5-gate via node N7. MT6-gate is connected to: MT3-source via node N6, MT3-gate via node N6, and MT4-drain via node N6. MT6-source is connected to: MT4-source, MT2-source, and node N4. The first s-bit generator is configured to generate an output A at node N7. The stochastic multiplier includes a second s-bit generator having plural memtransistors, comprising: a memtransistor, MT14, having a MT14-drain, a MT14-source, and a MT14-gate; a memtransistor, MT15, having a MT15-drain, a MT15-source, and a MT15-gate; a memtransistor, MT12, having a MT12-drain, a MT12-source, and a MT12-gate; a memtransistor, MT13, having a MT13-drain, a MT13-source, and a MT13-gate; a memtransistor, MT10, having a MT10-drain, a MT10-source, and a MT10-gate; and a memtransistor, MT1, having a MT11-drain, a MT11-source, and a MT1-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT14-drain is connected to: MT12-drain, MT10-drain, and VDD. MT14-gate is connected to node N12. MT14-source is connected to: MT15-drain and MT13-gate via node N11. MT15-drain is connected to MT13-gate via node N11. MT15-gate is connected to node N13. MT15-source is connected to: MT13-source, MT11-source, and GND. MT12-drain is connected to: MT14-drain, MT10-drain, and VDD). MT12-gate is connected to MT1-gate via node N10. MT12-source is connected to: MT1-gate via node N10 and MT13-drain via node N10. MT13-drain is connected to: MT12-source via node N10, MT12-gate via node N10, and MT1-gate via node N10. MT13-gate is connected to: MT14-source via node N11 and MT15-drain via node N11. MT13-source is connected to: MT14-source, MT11-source, and GND. MT10-drain is connected to: MT14-drain, MT12-drain, and VDD. MT10-gate is connected to MT11-drain via node N9. MT11-drain is connected to: MT10-source via node N9 and MT10-gate via node N9. MT1-gate is connected to: MT12-source via node N10, MT12-gate via node N10, and MT13-drain via node N10. MT11-source is connected to: MT13-source, MT15-source, and GND. The second s-bit generator is configured to generate an output B at node N9. The stochastic multiplier includes an AND gate configured to receive output A, receive output B, and generate an output C.
[0014]In some embodiments, the AND gate includes plural memtransistors, comprising: a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate; a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate; and a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate.
[0015]In some embodiments, for the first s-bit generator: output A is transmitted to the AND gate via node N7; node N7 is connected to MT7-gate; MT1-drain, MT3-drain, and MT5-drain are connected to MT7-drain; and MT2-source, MT4-source, and MT6-source are connected to: MT9-gate and to MT9-source. For the second s-bit generator: output B is transmitted to the AND gate via node N9; node N7 is connected to MT8-gate; MT10-drain, MT12-drain, and MT14-drain are connected to MT7-drain; and MT14-source, MT13-source, and MT11-source are connected to: MT9-gate and to MT9-source. For the AND gate: MT7-source is connected to MT8-drain; MT8-source connected to MT9-drain and to node N8; and the AND gate outputs C at node N8.
[0016]An exemplary embodiment relates to a stochastic adder. The stochastic adder includes a first s-bit generator having plural memtransistors, comprising: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate; a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: MT3-drain, MT5-drain, and node N1. MT1-gate is connected to node N2. MT1-source is connected to: MT2-drain and MT4-gate via node N5. MT2-drain is connected to MT4-gate via node N5. MT2-gate is connected to node N3. MT2-source is connected to: MT4-source, MT6-source, and node N4. MT3-drain is connected to: MT1-drain, MT5-drain, and node N1. MT3-gate is connected to MT6-gate via node N6. MT3-source is connected to: MT6-gate via node N6 and MT4-drain via node N6. MT4-drain is connected to: MT3-source via node N6, MT3-gate via node N6, and MT6-gate via node N6. MT4-gate is connected to: MT1-source via node N5 and MT2-drain via node N5. MT4-source is connected to: MT2-source, MT6-source, and node N4. MT5-drain is connected to: MT1-drain, MT3-drain, and node N1. MT5-gate is connected to MT6-drain via node N7. MT6-drain is connected to: MT5-source via node N7 and MT5-gate via node N7. MT6-gate is connected to: MT3-source via node N6, MT3-gate via node N6, and MT4-drain via node N6. MT6-source is connected to: MT4-source, MT2-source, and node N4. The first s-bit generator is configured to generate an output S. The stochastic adder includes a second s-bit generator having plural memtransistors, comprising: a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate; a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate; a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate; a memtransistor, MT10, having a MT10-drain, a MT10-source, and a MT10-gate; a memtransistor, MT1, having a MT11-drain, a MT11-source, and a MT1-gate; and a memtransistor, MT12, having a MT12-drain, a MT12-source, and a MT12-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT7-drain is connected to: MT9-drain, MT11-drain, and node VDD. MT7-gate is connected to node N8. MT7-source is connected to: MT8-drain and MT10-gate via node N10. MT8-drain is connected to MT10-gate via node N10. MT2-gate is connected to node N3. MT8-source is connected to: MT10-source, MT12-source, and GND. MT9-drain is connected to: MT7-drain, MT11-drain, and VDD). MT9-gate is connected to MT12-gate via node N11. MT9-source is connected to: MT12-gate via node N11 and MT10-drain via node N11. MT10-drain is connected to: MT9-source via node N11, MT9-gate via node N11, and MT12-gate via node N11. MT10-gate is connected to: MT7-source via node N10 and MT8-drain via node N10. MT10-source is connected to: MT8-source, MT12-source, and GND. MT11-drain is connected to: MT7-drain, MT9-drain, and VDD. MT1-gate is connected to MT12-drain via node N12. MT12-drain is connected to: MT11-source via node N12 and MT1-gate via node N12. MT12-gate is connected to: MT9-source via node N11, MT9-gate via node N11, and MT10-drain via node N11. MT12-source is connected to: MT10-source, MT8-source, and GND. The second s-bit generator is configured to generate an output A.
[0017]The stochastic adder includes a third s-bit generator having plural memtransistors, comprising: a memtransistor, MT13, having a MT13-drain, a MT13-source, and a MT13-gate; a memtransistor, MT14, having a MT14-drain, a MT14-source, and a MT14-gate; a memtransistor, MT15, having a MT15-drain, a MT15-source, and a MT15-gate; a memtransistor, MT16, having a MT16-drain, a MT16-source, and a MT16-gate; a memtransistor, MT17, having a MT17-drain, a MT17-source, and a MT17-gate; and a memtransistor, MT18, having a MT18-drain, a MT18-source, and a MT18-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT17-drain is connected to: MT15-drain, MT13-drain, and VDD. MT17-gate is connected to node N16. MT17-source is connected to: MT18-drain and MT16-gate via node N15. MT18-drain is connected to MT16-gate via node N15. MT18-gate is connected to node N17. MT18-source is connected to: MT16-source, MT14-source, and GND. MT15-drain is connected to: MT17-drain, MT13-drain, and VDD). MT15-gate is connected to MT14-gate via node N14. MT15-source is connected to: MT14-gate via node N14 and MT16-drain via node N14. MT16-drain is connected to: MT15-source via node N14, MT15-gate via node N14, and MT14-gate via node N14. MT16-gate is connected to: MT17-source via node N15 and MT18-drain via node N15. MT16-source is connected to: MT14-source, MT18-source, and GND. MT13-drain is connected to: MT17-drain, MT15-drain, and VDD). MT13-gate is connected to MT14-drain via node N13. MT14-drain is connected to: MT13-source via node N13 and MT13-gate via node N13. MT14-gate is connected to: MT15-source via node N14, MT15-gate via node N14, and MT16-drain via node N14. MT15-source is connected to: MT16-source, MT18-source, and GND. The third s-bit generator is configured to generate an output B. The stochastic adder includes MUX gate configured to receive output S, receive output A, receive output B, and generate an output C.
[0018]In some embodiments, the MUX gate includes plural memtransistors, comprising: a memtransistor, MT19, having a MT19-drain, a MT19-source, and a MT19-gate; a memtransistor, MT20, having a MT20-drain, a MT20-source, and a MT20-gate; a memtransistor, MT21, having a MT21-drain, a MT21-source, and a MT21-gate; and a memtransistor, MT22, having a MT22-drain, a MT22-source, and a MT22-gate.
[0019]In some embodiments, for the first s-bit generator: node N1 is connected to VDD; node N7 is connected to MT20-gate; and node N4 is connected to GND. For the second s-bit generator: MT7-drain, MT9-drain, and MT11-drain are connected to MT19-drain; and node N12 is connected to MT21-drain. For the third s-bit generator: node N13 is connected to MT22-source. For the MUX gate: MT19-drain is connected to N1 and VDD; MT19-gate is connected to: MT21-gate via node N18 and MT20-drain via node N18; MT19-source is connected to: MT21-gate via node N18 and MT20-drain via node N18; MT20-drain is connected to: MT19-gate via node N18, MT19-source via node N18, and MT21-gate via node N18; MT20-gate is connected to: node N7 and MT22-gate; MT20-source is connected to node N4 and GND; MT21-drain is connected to N12; MT21-gate is connected to: MT19-source via node N18, MT19-gate via node N18, and MT20-drain via node N18; MT21-source is connected to MT22-drain via node N19; MT22-drain is connected to MT21-source via node N19; MT22-gate is connected to MT20-gate; MT22-source is connected to node N13; and the MUX gate outputs C at node N19.
[0020]An exemplary embodiment relates to a stochastic subtractor. The stochastic subtractor includes a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B, wherein output A and output B are correlated bit streams. The stochastic subtractor includes an XOR gate, comprising plural memtransistors, the plural memtransistors including: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate; a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate; a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate; and a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate; a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: node N1, MT3-drain, MT5-drain, MT7-drain, and VDD). MT1-gate is connected to: MT7-gate and MT2-drain via node N2. MT1-source is connected to MT2-drain via node N2. MT2-drain is connected to: MT1-source via node N2 and MT1-gate via node N2. MT2-gate is connected to MT4-gate via node N4. MT2-source is connected to: MT9-gate via node N3 and GND. MT3-drain is connected to: node N1, MT1-drain, MT5-drain, MT7-drain, and VDD). MT3-gate is connected to: MT5-gate and MT6-drain via node N6. MT3-source is connected to MT4-drain. MT4-drain is connected to MT3-source. MT4-gate is connected to MT2-gate via node N4. MT4-source is connected to: MT9-drain via node N5 and MT8-source via node N5. MT5-drain is connected to: node N1, MT1-drain, MT3-drain, MT7-drain, and VDD). MT5-gate is connected to: MT3-gate and MT6-drain via node N6. MT5-source is connected to: MT3-gate via node N6 and MT6-drain via node N6. MT6-drain is connected to: MT5-source via node N6, MT5-gate via node N6, and MT3-gate via node N6. MT6-gate is connected to: MT8-gate via node N7. MT6-source is connected to: node N8 and GND. MT7-drain is connected to: node N1, MT1-drain, MT3-drain, MT5-drain, and VDD). MT7-gate is connected to: MT1-gate, MT1-source, and MT2-drain via node N2. MT7-source is connected to MT8-drain. MT8-drain is connected to MT7-source. MT8-gate is connected to MT6-gate via node N7. MT8-source is connected to MT9-drain via node N5. MT9-drain is connected to MT4-source via node N5 and MT8-source via node N5. MT9-gate is connected to: node N3 and GND. MT9-source is connected to: node N3 and GND. Output A is received at node N4 and output B is received at node N7. MT1 and MT2, together, act as a NOT gate to invert output A to generate output Ac. MT5 and MT6, together, act as a NOT gate to invert output B to generate Bc. The XOR gate is configured to receive output A, receive output B, and generate an output C via node N5.
[0021]An exemplary embodiment relates to a stochastic correlator, comprising: a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B, wherein output A and output B are uncorrelated bit streams. The stochastic correlator includes an OR gate, comprising plural memtransistors, the plural memtransistors including: a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate; a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate; a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate; Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. MT1-drain is connected to: node N1 and VDD. MT1-gate is connected to node N2. MT1-source is connected to: MT2-source, node N4, and MT3-drain. MT2-drain is connected to: node N1 and VDD. MT2-gate is connected to node N3. MT2-drain is connected to: MT1-source, node N4, and MT3-drain. MT3-drain is connected to MT1-source, MT2-source, and node N4. MT3-gate is connected to node N5 and GND. MT3-source is connected to GND. The OR gate is configured to receive output A at node N2, receive output B at node N3, and generate an output C via node N4.
[0022]An exemplary embodiment relates to a stochastic sorter. The stochastic sorter includes a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B. The stochastic sorter includes an OR gate configured to receive output A, receive output B, and generate an output C that is a maximum value of output A and output B. The stochastic sorter includes an AND gate configured to receive output A, receive output B, and generate an output D that is a minimum value of output A and output B.
[0023]Further features, aspects, objects, advantages, and possible applications of the present invention will become apparent from a study of the exemplary embodiments and examples described below, in combination with the Figures, and the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024]The above and other objects, aspects, features, advantages and possible applications of the present innovation will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. Like reference numbers used in the drawings may identify like components.
[0025]
[0026]
[0027]
[0028]
[0029]
[0030]
[0031]
[0032]
out-of-plane A1g modes at 304 cm−1 and 402 cm−1 respectively, with a peak-to-peak distance of ˜18 cm−1. Raman maps for (
and (
[0033]
[0034]
[0035]
[0036]
was found to be ˜80%
as a function of VBG. RTS is expected if the number of defects within the device falls into the red shaded area, the single defect limit as shown in
DETAILED DESCRIPTION OF THE INVENTION
[0037]The following description is of exemplary embodiments that are presently contemplated for carrying out the present invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles and features of the present invention. The scope of the present invention is not limited by this description.
[0038]An exemplary embodiment related to an s-bit generator 100. The s-bit generator 100 can include plural memtransistors 200 (e.g., 2D memtransistors), an inverting amplifier 300 (e.g., a differential amplifier in which the circuit's non-inverting input is grounded), and a programmable threshold inverter 400 (e.g., a circuit in which the output is switched from 0 to Vad when input is less than Vth such that for 0<Vin<Vth output is equal to logic 0 input and Vth<Vin<Vdd is equal to logic 1 input for inverter). One or more s-bits can be generated from inherent stochasticity in the plural 2D memtransistors. As can be appreciated from the disclosure herein, circuit topologies can be configured with the plural memtransistors 200 to provide the inverting amplifier 300 and/or the threshold inverter 400. For instance, in some embodiments, the s-bit generator 100 can consist of plural memtransistors 200, wherein some of the memtransistors 200 form the inverting amplifier 300 and/or the threshold inverter 400. Other embodiments of the s-bit generator 100 can have inverting amplifier 300 and/or the threshold inverter 400 that is/are not formed by memtransistors 200.
[0039]Inherent stochasticity in the plural 2D memtransistors 200 can include one or more of: cycle-to-cycle fluctuations in carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor of the plural 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors, and/or random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors.
[0040]Referring to
[0041]As shown in
[0042]In an exemplary embodiment, MT1-drain can be connected to: MT3-drain, MT5-drain, and node N1. MT1-gate can be connected to node N2. MT1-source can be connected to: MT2-drain and MT4-gate via node N5. MT2-drain can be connected to MT4-gate via node N5. MT2-gate can be connected to node N3. MT2-source can be connected to: MT4-source, MT6-source, and node N4. MT3-drain can be connected to: MT1-drain, MT5-drain, and node N1. MT3-gate can be connected to MT6-gate via node N6. MT3-source can be connected to: MT6-gate via node N6 and MT4-drain via node N6. MT4-drain can be connected to: MT3-source via node N6, MT3-gate via node N6, and MT6-gate via node N6. MT4-gate can be connected to: MT1-source via node N5 and MT2-drain via node N5. MT4-source can be connected to: MT2-source, MT6-source, and node N4. MT5-drain can be connected to: MT1-drain, MT3-drain, and node N1. MT5-gate can be connected to MT6-drain via node N7. MT6-drain can be connected to: MT5-source via node N7 and MT5-gate via node N7. MT6-gate can be connected to: MT3-source via node N6, MT3-gate via node N6, and MT4-drain via node N6. MT6-source can be connected to: MT4-source, MT2-source, and node N4.
[0043]In some embodiments, the 2D channel is a monolayer.
[0044]In some embodiments, the monolayer includes MoS2.
[0045]Referring to
[0046]In some embodiments, the stochastic computing processor can have a non-von Neuman architecture. A von Neumann architecture generally consists of a single, shared memory for programs and data, a single bus for memory access, an arithmetic unit, and a program control unit. A non-von Neumann architecture deviates from this arrangement.
[0047]Any of the processors 106 disclosed herein can be part of or in communication with a machine (e.g., a computer device, a logic device, a circuit, an operating module (hardware, software, and/or firmware), etc.). The processor 106 can be hardware (e.g., processor, integrated circuit, central processing unit, microprocessor, core processor, computer device, etc.), firmware, software, etc. configured to perform operations by execution of instructions embodied in computer program code, algorithms, program logic, control, logic, data processing program logic, artificial intelligence programming, machine learning programming, artificial neural network programming, automated reasoning programming, etc. The processor 106 can receive, process, and/or store data.
[0048]Any of the processors 106 disclosed herein can be a scalable processor, a parallelizable processor, a multi-thread processing processor, etc. The processor 106 can be a computer in which the processing power is selected as a function of anticipated network traffic (e.g. data flow). The processor 106 can include any integrated circuit or other electronic device (or collection of devices) capable of performing an operation on at least one instruction, which can include a Reduced Instruction Set Core (RISC) processor, a Complex Instruction Set Computer (CISC) microprocessor, a Microcontroller Unit (MCU), a CISC-based Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), etc. The hardware of such devices may be integrated onto a single substrate (e.g., silicon “die”), or distributed among two or more substrates. Various functional aspects of the processor may be implemented solely as software or firmware associated with the processor 106.
[0049]The processor 106 can include one or more processing or operating modules. A processing or operating module can be a software or firmware operating module configured to implement any of the functions disclosed herein. The processing or operating module can be embodied as software and stored in memory 108, the memory 108 being operatively associated with the processor 106. A processing module can be embodied as a web application, a desktop application, a console application, etc.
[0050]The processor 106 can include or be associated with a computer or machine readable medium. The computer or machine readable medium can include memory 108. Any of the memory 108 discussed herein can be computer readable memory configured to store data. The memory 108 can include a volatile or non-volatile, transitory or non-transitory memory, and be embodied as an in-memory, an active memory, a cloud memory, etc. Examples of memory 108 can include flash memory, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read only Memory (PROM), Erasable Programmable Read only Memory (EPROM), Electronically Erasable Programmable Read only Memory (EEPROM), FLASH-EPROM, Compact Disc (CD)-ROM, Digital Optical Disc DVD), optical storage, optical medium, a carrier wave, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by the processor 106.
[0051]The memory 108 can be a non-transitory computer-readable medium. The term “computer-readable medium” (or “machine-readable medium”) as used herein is an extensible term that refers to any medium or any memory 108, that participates in providing instructions to the processor for execution, or any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). Such a medium may store computer-executable instructions to be executed by a processing element and/or control logic, and data which is manipulated by a processing element and/or control logic, and may take many forms, including but not limited to, non-volatile medium, volatile medium, transmission media, etc. The computer or machine readable medium can be configured to store one or more instructions thereon. The instructions can be in the form of algorithms, program logic, etc. that cause the processor 106 to execute any of the functions disclosed herein.
[0052]Embodiments of the memory 108 can include a processor module and other circuitry to allow for the transfer of data to and from the memory 108, which can include to and from other components of a communication system. This transfer can be via hardwire or wireless transmission. The communication system can include transceivers, which can be used in combination with switches, receivers, transmitters, routers, gateways, wave-guides, etc. to facilitate communications via a communication approach or protocol for controlled and coordinated signal transmission and processing to any other component or combination of components of the communication system. The transmission can be via a communication link. The communication link can be electronic-based, optical-based, opto-electronic-based, quantum-based, etc. Communications can be via Bluetooth, near field communications, cellular communications, telemetry communications, Internet communications, etc.
[0053]Transmission of data and signals can be via transmission media. Transmission media can include coaxial cables, copper wire, fiber optics, etc. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications, or other form of propagated signals (e.g., carrier waves, digital signals, etc.).
[0054]Any of the processors 106 can be in communication with other processors of other devices (e.g., a computer device, a computer system, a laptop computer, a desktop computer, etc.). Any of the processors 106 can have transceivers or other communication devices/circuitry to facilitate transmission and reception of wireless signals. Any of the processors 106 can include an Application Programming Interface (API) as a software intermediary that allows two or more applications to talk to each other.
[0055]Referring to
[0056]In some embodiments, the AND gate 112 can include plural memtransistors, comprising: a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate; a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate; and a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate.
[0057]For the first s-bit generator 100: output A is transmitted to the AND gate 112 via node N7; node N7 is connected to MT7-gate; MT1-drain, MT3-drain, and MT5-drain are connected to MT7-drain; and MT2-source, MT4-source, and MT6-source are connected to: MT9-gate and to MT9-source. For the second s-bit generator 100: output B is transmitted to the AND gate via node N9; node N7 is connected to MT8-gate; MT10-drain, MT12-drain, and MT14-drain are connected to MT7-drain; and MT14-source, MT13-source, and MT11-source are connected to: MT9-gate and to MT9-source. For the AND gate 112: MT7-source is connected to MT8-drain; MT8-source connected to MT9-drain and to node N8; and the AND gate outputs C at node N8.
[0058]Referring to
[0059]The stochastic adder 114 can include a third s-bit generator having plural memtransistors, comprising: a memtransistor, MT13, having a MT13-drain, a MT13-source, and a MT13-gate; a memtransistor, MT14, having a MT14-drain, a MT14-source, and a MT14-gate; a memtransistor, MT15, having a MT15-drain, a MT15-source, and a MT15-gate; a memtransistor, MT16, having a MT16-drain, a MT16-source, and a MT16-gate; a memtransistor, MT17, having a MT17-drain, a MT17-source, and a MT17-gate; and a memtransistor, MT18, having a MT18-drain, a MT18-source, and a MT18-gate. Each memtransistor can be stacked on a non-volatile and programmable local back-gate stack. Each memtransistor can have a 2D channel formed between its source and its drain. MT17-drain can be connected to: MT15-drain, MT13-drain, and VDD. MT17-gate can be connected to node N16. MT17-source is connected to: MT18-drain and MT16-gate via node N15. MT18-drain can be connected to MT16-gate via node N15. MT18-gate can be connected to node N17. MT18-source can be connected to: MT16-source, MT14-source, and GND. MT15-drain can be connected to: MT17-drain, MT13-drain, and VDD. MT15-gate is connected to MT14-gate via node N14. MT15-source can be connected to: MT14-gate via node N14 and MT16-drain via node N14. MT16-drain i can be connected to: MT15-source via node N14, MT15-gate via node N14, and MT14-gate via node N14. MT16-gate can be connected to: MT17-source via node N15 and MT18-drain via node N15. MT16-source can be connected to: MT14-source, MT18-source, and GND. MT13-drain can be connected to: MT17-drain, MT15-drain, and VDD. MT13-gate can be connected to MT14-drain via node N13. MT14-drain can be connected to: MT13-source via node N13 and MT13-gate via node N13. MT14-gate can be connected to: MT15-source via node N14, MT15-gate via node N14, and MT16-drain via node N14. MT15-source can be connected to: MT16-source, MT18-source, and GND. The third s-bit generator 100 can be configured to generate an output B. The stochastic adder 114 can include a MUX gate 116 configured to receive output S, receive output A, receive output B, and generate an output C.
[0060]In some embodiments, the MUX gate 116 can include plural memtransistors, comprising: a memtransistor, MT19, having a MT19-drain, a MT19-source, and a MT19-gate; a memtransistor, MT20, having a MT20-drain, a MT20-source, and a MT20-gate; a memtransistor, MT21, having a MT21-drain, a MT21-source, and a MT21-gate; and a memtransistor, MT22, having a MT22-drain, a MT22-source, and a MT22-gate.
[0061]For the first s-bit generator 100: node N1 is connected to VDD; node N7 is connected to MT20-gate; and node N4 is connected to GND. For the second s-bit generator 100: MT7-drain, MT9-drain, and MT11-drain are connected to MT19-drain; and node N12 is connected to MT21-drain. For the third s-bit generator 100: node N13 is connected to MT22-source. For the MUX gate 116: MT19-drain is connected to N1 and VDD; MT19-gate is connected to: MT21-gate via node N18 and MT20-drain via node N18; MT19-source is connected to: MT21-gate via node N18 and MT20-drain via node N18; MT20-drain is connected to: MT19-gate via node N18, MT19-source via node N18, and MT21-gate via node N18; MT20-gate is connected to: node N7 and MT22-gate; MT20-source is connected to node N4 and GND; MT21-drain is connected to N12; MT21-gate is connected to: MT19-source via node N18, MT19-gate via node N18, and MT20-drain via node N18; MT21-source is connected to MT22-drain via node N19; MT22-drain is connected to MT21-source via node N19; MT22-gate is connected to MT20-gate; MT22-source is connected to node N13; and the MUX gate 116 outputs C at node N19.
[0062]Referring to
[0063]Referring to
[0064]Referring to
[0065]Referring to
EXAMPLES
[0066]The following discussion relates to exemplary implementations of embodiments of the devices, systems, circuits, and methods disclosed herein. It is understood that the following examples demonstrate exemplary implementations, and embodiments of the devices, systems, circuits, and methods disclosed herein are not meant to be limited to these examples.
[0067]As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence, deep learning, and Big-data, a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, makes it less attractive. Memristor and spin-based devices offer natural randomness, but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Embodiments disclosed herein overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors.
[0068]Embodiments of the monolithic and non-von Neumann SC architecture consume a miniscule amount of energy <1 nano Joules for s-bit generation and to perform arithmetic operations and occupy small hardware footprint highlighting the benefits of SC.
[0069]Stochastic computing (SC) is an attractive alternative, where arithmetic operations can be performed using simple logic gates yielding high energy and area efficiency. For example, a simple two-bit multiplication in a conventional CMOS based full adder circuit requires 78 transistors whereas a SC unit can execute the same operation using a single AND gate. Similarly, stochastic addition and subtraction can be performed using multiplexer (MUX) and XOR gates, respectively. The key difference is that unlike classical computing system which represents information in the form of binary logic (‘1’s and ‘0’s), SC encodes information through stochastic bit (s-bit) streams that are interpreted as probabilities that fall in the interval [0,1]. For instance, the bit-stream A={1 0 1 1 0 1 0 0} encodes the value ρA=0.5 since there are four 1's present within the bit-stream of length 8-bit. An attractive feature of SC is its resilience to error tolerance since there is no distinction between the most and the least significant bits, or in other words all s-bits carry equal weight. While promising, the application of SC has largely been limited to specialized domains such as image and audio processing where a finite amount of error or loss in precision is acceptable. Such limitations primarily stem from the requirement of having a much longer bit-stream for more accurate probability estimation that leads to a corresponding increase in the computation time and energy. Despite these shortcomings, SC is becoming popular for many AI applications, which deal with large volumes of audio-visual information. Note that the idea of SC is also rooted in bio-inspired computing since the brain can process information in the presence of noise, and can learn, adapt, and make right decisions to ensure the survival of the species at the cost of miniscule energy expenditure.
[0070]The concept of SC is well known and extensively studied. CMOS, memristor, and spintronics based SC architectures have already been demonstrated in the past. However, CMOS-based SC architectures require several hundred transistors to generate s-bits, which limits its area and energy efficiency. Stochastic switching in memristors offer an excellent mechanism to generate fast and random bits with the added benefits of high integration density since memristors can be scaled down to sub 10 nm. However, memristor-based SC architectures still require CMOS peripherals to control the probability of switching for the conversion of random bits into s-bits and for subsequent logic operations using those s-bits, which can ultimately limit the area and energy efficiency. Recently, spin-based magnetic random access memory (MRAM) devices and spin-orbit torque magnetic tunnel junctions (SOT-MTJ) have shown immense potential for SC since the probability of spin-flip can be controlled by externally driven current allowing seamless generation of s-bits. In addition, spin-based devices offer high switching speed, a simpler structure, high throughput, and better area and energy efficiency and are therefore, fundamentally superior in performance to CMOS-based alternatives. However, environmental, and electrical fluctuations can interfere and impact the spin-flip probability necessitating additional CMOS-based peripheral circuits to remove the bias. Although, recent demonstration of integer factorization using spin-based MRAM devices is a milestone achievement, the SC architecture utilized for such demonstration involves extensive CMOS peripherals since two-terminal MRAM devices suffer from similar limitations like the memristors.
[0071]Embodiments disclosed herein overcome the above-mentioned limitations by introducing a standalone SC architecture embedded in memory, which is based on two dimensional (2D) memtransistors. Memtransistors are programmable field effect transistors (FETs) made from ultra-thin body semiconducting channel material such as monolayer MoS2 allowing aggressive channel length scaling owing to superior gate electrostatics. Our main contributions are 1) the realization of an area and energy efficient six-transistor (6T) s-bit generator circuit that exploits the inherent stochasticity in the carrier trapping and detrapping phenomena in the gate insulator of the 2D memtransistors and combines it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits and 2) integration of s-bit generators with 2D memtransistor based logic gates such as AND, MUX, XOR, and OR gates to demonstrate arithmetic operations such as addition, subtraction, multiplication, and sorting.
Fabrication and Characterization of 2D Memtransistors
[0072]
[0073]As expected, n-type transport is observed in MoS2, which is attributed to the pinning of the metal Fermi level near the conduction band. Nevertheless, MoS2 memtransistor exhibits excellent electrostatic gate control with current on/off ratio (rON/OFF) ˜106, subthreshold slope (SS) ˜370 m V/decade averaged over 4 orders of magnitude change in IDS, minimal gate hysteresis when measured in air, and low gate leakage current. The threshold voltage (VTH) was found to be ˜2 V extracted at iso-current of 100 nA/μm and the electron field effect mobility (μFE) extracted from the peak trans-conductance was found to be ˜5 cm2/V−s.
[0074]Finally,
Programming Stochasticity in 2D Memtransistor and s-Bit Generation
[0075]Generation of high-quality random bits is a pre-requisite for reducing computational inaccuracies at the output of any stochastic operation. Here, we exploit the inherent stochasticity in the carrier trapping and detrapping phenomena in the gate oxide of the 2D memtransistor as the source of true randomness.
[0076]In order to translate the conductance fluctuation into s-bits, we deploy a module having six memtransistors (MT1, MT2, MT3, MT4, MT5, and MT6) as shown using the optical image and corresponding circuit diagram in
[0077]Next the Gaussian distribution is broadened by using an inverting amplifier constructed using MT3 and MT4. Note that the local back-gate of MT3 is shorted to its source at node, N6. This ensures that MT3 operates as a depletion mode (normally on) transistor or as a load resistor.
[0078]To transform the analog fluctuations seen in VN6 into s-bits, we use a thresholding inverter constructed using MT5 and MT6.
[0079]The average energy expenditure for s-bit generation (Es-bit) was calculated using:
CG is the gate capacitance, ININ4-i is the current flowing through the s-bit generator during each τclk, ε0=8.85×10−12 F/m is the vacuum permittivity, and ε0X=10, and t0=50 nm are, respectively, the relative permittivity and thickness of Al2O3. We found that Es-bit <2 pJ/clock-cycle, which supports our claim on energy efficient s-bit generation. Note that the second term in the equation is more than three orders of magnitude smaller, ˜1 fJ (we have used N=100 to calculate the average current in the s-bit generator per clock cycle). Therefore, it is possible to reduce the energy expenditure even further through scaling of t0x which will scale the program/erase voltages accordingly. Also note that each memtransistor has an active device area that is ˜5 μm2 excluding the large contact pads. Therefore, the active footprint of the s-bit generator is only 30 μm2. Given that monolayer 2D materials offer aggressive dimensional scalability, it is possible to reduce the active footprint significantly without compromising the quality of the s-bits.
Stochastic Arithmetic Modules
Multiplication:
[0080]Stochastic multiplication can be accomplished using a simple AND gate as shown in
pA pB, and pC, are the probabilities associated with the random variables, A, B, and C respectively. These equations are valid if and only if the random variables, A and B, are mutually independent or uncorrelated.
[0081]
(pC)obtained and (pC)expected are the experimentally obtained and theoretically predicted output of the stochastic computation.
[0082]As mentioned earlier, to obtain accurate multiplication product, A and B must be mutually independent.
Addition:
[0083]Stochastic addition operation can be accomplished using a MUX as shown in
[0084]Clearly, for ps=0.5, one can achieve scaled addition.
Subtraction:
[0085]While the circuits used for stochastic multiplication and addition require the stochastic inputs to be independent or uncorrelated to achieve accurate results, stochastic subtraction benefits greatly from the correlation between the stochastic inputs. In fact, correlated inputs can drastically alter the functionality of a stochastic circuit thereby simplifying the hardware acceleration of specific arithmetic operations. For example, if a XOR gate (
[0086]However, when A and B are highly correlated, it implements absolute-valued subtraction:
[0087]As an example, if A=01110110 and B=011000100 are two correlated stochastic streams representing pA=5/8 and pB=3/8, then C=00010010 and pC=2/8. Note that conventional implementation of this function requires one NOT gate, one 2×1 MUX, and one finite state machine (FSM), increasing the area and energy overhead.
[0088]
[0089]While the s-bit generators produce uncorrelated bit-streams, correlated random variables can be created by using an OR gate as shown in
Sorting:
[0090]As we have shown earlier, an AND gate functions as a stochastic multiplier for uncorrelated bit-streams. However, when the inputs become highly correlated, it gives the minimum of the two stochastic streams. As an example, if A=01101110 and B=01100100 are two correlated stochastic streams representing pA=5/8 and pB=3/8, then C=01100100 and pC=3/8. Similarly, an OR gate, gives the maximum value of two stochastic streams, e.g., C=01101110 and pC=5/8. This is in contrast to conventional implementation with uncorrelated inputs that require FSM-based stochastic hyperbolic tangent (tanh) function along with the three MUXs, which again increases area and energy overhead.
[0091]Table 1 summarizes the SC architectures for different arithmetic operations involving medium scale integration (MSI) of 2D memtransistors along with their respective energy expenditure.
| TABLE 1 |
|---|
| Summary of the SC architecture for different arithmetic operations |
| Average | ||||
| # of s-bit | Logic | energy | ||
| Arithmetic operation | generators | gates | # of memtransistors | expenditure |
| Multiplication | 2 | AND | 15 | ~0.8 nJ |
| Addition | 3 | 2 × 1 MUX | 22 | ~1.2 nJ |
| Subtraction | 2 | XOR | 24 | ~0.8 nJ |
| (correlated s-bits) | (including correlator circuit) | |||
| Sorting | 2 | OR, AND | 21 | ~0.8 nJ |
| (correlated s-bits) | (including correlator circuit) | |||
[0092]It is contemplated to expand the SC architecture to accelerate Bayesian neural networks, invertible logic, and solve various combinatorial optimization problems such as the traveling salesman problem. While it is contemplated to realize all peripherals using 2D memtransistors, 2D memtransistor-based stochastic computing hardware can benefit in the short-term from integration with mature Si CMOS technology. In fact, it is possible that the 2D memtransistor and CMOS technology can synergistically co-exist. Also note that very large-scale integration (VLSI) of 2D memtransistors is non-trivial as multiple challenges must be overcome. While there has been tremendous progress on large-area growth of a wide range of 2D materials, there is still scope to minimize growth defects to achieve higher performance and increase growth uniformity to ensure low device-to-device variation. At the same time, large area transfer of 2D materials must be improved for cleaner and mechanical damage-free transfer ensuring high yield during device fabrication. Finally, the future roadmap for 2D memtransistors will involve scaling of channel length and oxide thickness. While earlier experimental reports and theoretical projections from literature do indicate that 2D material-based field effect transistors (FETs) can meet the requirements set forth by the International Roadmap for Devices and Systems (IRDS 2028), programmability of scaled memtransistors may need to be investigated further.
[0093]As can be appreciated from the disclosure presented herein, the cycle-to-cycle variability in the programmed conductance of monolayer MoS2 based 2D memtransistors can be exploited and translated the same into s-bits with reconfigurable probability of obtaining ‘1’ in the bit-stream using a s-bit generator circuit comprising of 6 memtransistors and subsequently combined the s-bit generator with 2D memtransistor based logic gates to demonstrated a standalone SC architecture that can perform accurate arithmetic operations such as addition, subtraction, multiplication, and sorting. The SC architecture consumes miniscule energy ˜1 nano Joules to perform arithmetic operations and uses limited numbers of memtransistors with small active-area footprint. Embodiments herein offer a way to accelerate SC on a non-von Neumann platform based on novel 2D materials and devices.
Methods
Fabrication of Local Back-Gate Islands:
[0094]To define the back-gate island regions, the substrate 285 nm SiO2 on p++-Si was spin coated with bilayer photoresist consisting of Lift-Off-Resist (LOR 5A) and Series Photoresist (SPR 3012) baked at 185° C. and 95° C., respectively. The bilayer photoresist was then exposed to Heidelburg Maskless Aligner (MLA 150) to define the island and developed using MF CD26 microposit, followed by a de-ionized (DI) water rinse. The back gate electrode of 20/50 nm TiN/Pt was deposited using reactive sputtering. The photoresist was removed using acetone and Photo Resist Stripper (PRS 3000) and cleaned using 2-propanol (IPA) and DI water. Atomic layer deposition (ALD) process was then implemented to grow 50 nm Al2O3 on the entire substrate including the island regions. To access the individual Pt back-gate electrodes etch patterns were defined using the same bilayer photoresist consisting of LOR 5A and SPR 3012. The bilayer photoresist was then exposed to MLA 150 and developed using MF CD26 microposit. 50 nm Al2O3 was subsequently dry etched using the BCl3 chemistry at 5° C. for 20 seconds, which was repeated four times to minimize heating in the substrate. Next, the photoresist was removed to give access to the individual Pt electrodes.
Large Area Monolayer MoS 2 Film Growth:
[0095]Monolayer MoS2 was deposited on epi-ready 2″ c-sapphire substrate by metalorganic chemical vapor deposition (MOCVD). An inductively heated graphite susceptor equipped with wafer rotation in a cold-wall horizontal reactor was used to achieve uniform monolayer deposition as previously described. Molybdenum hexacarbonyl (Mo(CO)6) and hydrogen sulfide (H2S) were used as precursors. Mo(CO)6 maintained at 10° C. and 650 Torr in a stainless-steel bubbler was used to deliver 1.1×10−3 sccm of the metal precursor for the growth, while 400 sccm of H2S was used for the process. MoS2 deposition was carried out at 1000° C. and 50 Torr in H2 ambient, where monolayer growth was achieved in 18 min. The substrate was first heated to 1000° C. in H2 and maintained for 10 min before the growth was initiated. After growth, the substrate was cooled in H2S to 300° C. to inhibit decomposition of the MoS2 films.
MoS 2 Film Transfer to Local Back-Gate Islands:
[0096]To fabricate the 2D memtransistors, MOCVD grown monolayer MoS2 film was transferred from the sapphire to SiO2/p++-Si substrate with local back-gate islands using PMMA (polymethyl-methacrylate) assisted wet transfer process. First, MoS2 on sapphire substrate was spin coated with PMMA and then baked at 180° C. for 90 s. The corners of the spin-coated film were scratched using a razor blade and immersed inside 1 M NaOH solution kept at 90° C. Capillary action causes the NaOH to be drawn into the substrate/film interface, separating the PMMA/MoS2 film from the sapphire substrate. The separated film was rinsed multiple times inside a water bath and finally transferred onto the SiO2/p++-Si substrate with local back-gate islands and then baked at 50° C. and 70° C. for 10 min each to remove moisture and residual PMMA, ensuring a pristine interface.
Fabrication of 2D Memtransistors:
[0097]To define the channel regions for the memtransistors, the substrate was spin-coated with PMMA and baked at 180° C. for 90 s. The resist was then exposed to electron beam (e-beam) and developed using 1:1 mixture of 4-methyl-2-pentanone (MIBK) and 2 propanol (IPA). The monolayer MoS2 film was subsequently etched using sulfur hexafluoride (SF6) at 5° C. for 30 s. Next, the sample was rinsed in acetone and IPA to remove the e-beam resist. To define the source and drain contacts, sample is then spin coated with methyl methacrylate (MMA) followed by A3 PMMA. Then using e-beam lithography source and drain contacts are patterned and developed by using 1:1 mixture of MIBK and IPA for 60s. 40 nm of Nickel (Ni) and 30 nm of Gold (Au) are deposited using e-beam evaporation. Finally, lift-off process is performed to remove the evaporated Ni/Au except from the source/drain patterns by immersing the sample in acetone for 30 min followed by IPA for another 30 mins. Each island contains one memtransistor to allow for individual gate control.
Monolithic Integration:
[0098]To define the connections between the respective memtransistors the substrate was spin coated with MMA and PMMA, followed by the e-beam lithography and developing using 1:1 mixture of MIBK and IPA, and e-beam evaporation of 60 nm Au. Finally, the e-beam resist was rinsed away by lift-off process using acetone and IPA.
Electrical Characterization:
[0099]Electrical characterization of the fabricated devices is performed using Lake Shore CRX-VF probe station under atmospheric condition using a Keysight B1500A parameter analyzer.
Observation of Rich Defect Dynamics in Monolayer MoS 2
[0100]Defects play a pivotal role in limiting the performance and reliability of most nanoscale devices. Field effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors such as monolayer MoS2 are no exceptions. Probing defect dynamics in 2D FETs is, therefore, of significant interest. This study presents a comprehensive insight into various defect dynamics observed in monolayer MoS2 FETs at varying gate biases and temperatures. The measured source to drain currents exhibit random telegraph signals (RTS) owing to the transfer of charges between the semiconducting channel and individual defects. Based on the modeled temperature and gate bias dependence, oxygen vacancies or aluminum interstitials are probable defect candidates. Several types of RTSs are observed including anomalous RTS and giant RTS indicating local current crowding effects and rich defect dynamics in monolayer MoS2 FETs. This study explores defect dynamics in large area-grown monolayer MoS2 with ALD-grown Al2O3 as the gate dielectric.
[0101]According to the International Roadmap for Devices and Systems (IRDS), atomically thin and semiconducting transition metal dichalcogenides (TMDCs) such as monolayer MoS2 are promising alternatives to silicon for both low-power and high-performance logic devices at advanced technology nodes. Recent developments in high-performance field effect transistors (FETs) based on large-area synthesized monolayer MoS2 and demonstration of integrated circuits for digital, analog, radio frequency (RF), and brain-inspired electronics justify its inclusion in the IRDS. Unsurprisingly, most studies on MoS2 FETs focus on improvement in large area growth, optimization of transfer and fabrication process flow, contact and mobility engineering, the realization of scaled devices, etc., to meet the theoretical performance limit predicted by numerical simulations. However, less emphasis is laid on understanding the nature and origin of defects in MoS2 FETs, which can ultimately limit performance and raise reliability concerns.
[0102]Defects in MoS2 FETs can reside in the semiconducting channel such as sulfur vacancies, at the channel/dielectric interface, or in the dielectric stack. Their origin can be ascribed to growth imperfection, film transfer, fabrication processes, and fundamental properties of the gate dielectrics and their distinct defect bands. During device operation, these defects can exchange charges with the channel, affecting the device performance and reliability. Most reliability studies on MoS2 FETs involve the investigation of bias temperature instabilities (BTI), which occur due to charge trapping in the oxide or at the trapping sites introduced by adsorbates and water molecules at the interface. Charge trapping can lead to a decrease in the field effect mobility, worsening of the subthreshold slope, hysteresis in the device transfer characteristics, as well as permanent or partially recoverable threshold voltage shifts.
[0103]Whereas BTI is a useful approach to studying the reliability of 2D FETs, a better understanding of the physical mechanisms of charge trapping and the nature of the involved defects can be obtained via the characterization of individual defects. Such characterization, however, requires ultra-scaled devices, which contain only a few defects within the channel area. In particular, when a single defect dominates the device response, discrete steps can be observed in the measured source to drain currents resulting in a random telegraph signal (RTS). Statistical analysis of RTS allows for the extraction of the capture and emission time constants, trap level, activation energy, and even the physical location of the defects offering insights into the microscopic properties of the defects.
[0104]Stampfer, B. et al. observed RTS from single defects in scaled FETs based on exfoliated multilayer MoS2 with 50 nm×50 nm channel area. They found these defects are located either in the bulk SiO2, which was used as the back gate dielectric, or at the SiO2/MoS2 interface, or on top of the channel arising from adsorbed water molecules and processing contaminants. Fang, N et al. and Li, L. et al. were also able to observe RTS in exfoliated mono- and multilayer MoS2 FETs despite relatively large channel area (˜10-100 μm2), but at low temperatures <100 K. Interestingly, to the best of our knowledge, there is no report of observation of RTS in large area synthetic monolayer MoS2 FETs, although previous works involving high-resolution transmission electron microscopy (TEM) and scanning tunneling microscopy (STM) have suggested sulfur monovacancies as the most abundant defect type in synthetic MoS2.
[0105]This study reports the observation of RTS in metal-organic chemical vapor deposition (MOCVD) grown monolayer MoS2-based FETs at varying gate biases and temperatures. By modeling the bias- and temperature dependence of the capture and emission time constants with a non-radiative multi-phonon model (NMP), possible defect candidates for the charge trapping in the Al2O3 gate oxide and their electronic and vibrational properties are identified. Several types of RTS are observed including anomalous RTS and giant RTS indicating local current crowding effects and rich defect dynamics in synthetic monolayer MoS2 FETs using Al2O3 as a gate dielectric.
Characterization of MOCVD-Grown Monolayer MoS 2 Films
[0106]
out-of-plant A1g Hours at 384 cm−1 and 402 cm−1 respectively, with a peak-to-peak distance of ˜18 cm−1. Raman maps for (
and (
[0107]The monolayer MoS2 utilized for this study was grown using MOCVD on 1 cm2 c-plane sapphire substrates at a temperature of 1000° C. To ascertain the quality of the MoS2 film used in this study, material characterization was performed using Raman spectroscopy and atomic force microscopy (AFM).
mode and out-of-plant A1g mode was observed at 384 cm−1 and 402 cm−1 respectively, with a peak-to-peak distance of ˜18 cm−1.
and A1g peak positions measured over a 50 μm×50 μm area, respectively. The mean and standard deviation values for
and A1g were found to be ˜383.7 cm−1 and ˜0.17 cm−1 and ˜401.8 cm−1 and 0.14 cm−1, respectively.
Fabrication and Characterization of Monolayer MoS 2 FETs
[0108]Monolayer MoS2 FETs employed for this study use a global back-gated architecture with 50 nm atomic layer deposition grown Al2O3 as the gate dielectric, and Pt/TiN/p++-Si as the back-gate electrode.
Observation of RTS in Monolayer MoS 2 FETs
[0109]
[0110]The impact of individual defects on silicon-based field effect transistors (FETs) has been extensively studied. It is well known that the capture and emission of charges by the defect sites lead to a shift in the threshold voltage (VTH) of the device, which manifests as hysteresis in the FET transfer characteristics. The stochastic nature of charge carrier capture and emission can lead to temporal fluctuations in the source-to-drain current when measured at constant source-to-gate and source-to-drain biases. In fact, discrete steps can be observed in IDS if only a handful of defects are present in the channel area and cause notable changes in the electrostatics of the device. Such an IDS profile is referred to as RTS. This is generally the case in ultra-scaled devices where a reduction in the channel area leads to the confinement of a few defects with each defect having a considerable impact on the device characteristics. RTS can also be observed in relatively large-area devices when measured at low temperatures. This can be attributed to the fact that only a few defect states are energetically accessible for the charge carriers at low temperatures and that the current flow can be locally constrained, thereby causing sizable step heights.
[0111]
[0112]Another way to visualize the presence of RTS is to plot the histograms of the measured IDS as shown in
[0113]To overcome the aforementioned challenge, Nagumo et. al have outlined the use of a Time Lag Plot (TLP). A TLP involves the plotting of time-domain IDS data in an x-y plane, where the x-values represent the ith and the y-values represent the i+1th time series data for IDS.
[0114]A central drawback of the histogram and TLP methods is their reliance on absolute values of the signal for obtaining defect states. For example, a small drift of the drain current level over time can easily obfuscate defect states with smaller step heights, reducing the overall number of detected defects. Furthermore, both methods require a relatively high signal-to-noise ratio to work. To overcome these difficulties, edge detection algorithms can be used to obtain the positions and amplitudes of the discrete steps in the RTS. In this work, the Canny edge-detection algorithm was used to detect step edges based on a Gaussian derivative as a filter function.
Gate-Bias-Dependent RTS for Extracting the Physical Location of Defects
[0115]
[0116]Further insights into the defect dynamics can be obtained by studying the impact of VBG on the RTS.
ET is the energy level of the trap and k is the Boltzmann constant.
We found that λ2˜1.2 nm from the interface.
[0117]As a next step, we have applied the Canny algorithm and the formalism to extract the capture and emission time constants as described above to analyze the time constants as a function of the gate bias and the temperature as shown in
Modeling RTS for Extracting the Vibronic Defect Properties
[0118]
[0119]For learning more about the atomic nature of the defect, we model the temperature and bias dependence of the capture and emission time constants using the NMP model. When an electron is exchanged between a charge reservoir, like the conduction band of MoS2, and a local point defect in the vicinity, this charge transfer is accompanied by local deformations and relaxations of the defect sites. Hence, for accurately modeling RTS, electron-phonon coupling must be described, accounting for both the movement of electrons and nuclei. The atomic movements are represented within diabatic potential energy curves (i.e., crossing potential energy surfaces at a fixed charge state) along the reaction path of the charge transfer reaction. Such a configuration coordinate diagram for an oxide defect is shown in
with the surface potential ΨS, an expression that is equivalent to
under the assumption of a constant surface potential in accumulation.
[0120]In the following, we evaluate this expression by modeling the temperature dependence of the capture and emission time constants for varying gate biases in a full quantum mechanical NMP model. The background, assumptions, and derivation of this model are described in more detail in the Methods section. The NMP transition rates are the inverse of the experimentally determined capture and emission time constants kC=1/τc=kij and are given by,
with the electronic wave functions Φi, Φj, the vibrational states ηi.α, ηi.β, describing the nuclei configurations, the electronic matrix element Aij determined by the electronic Hamiltonian Hel, and the line-shape function
governing the vibrational interactions. Aij can, in good approximation, be evaluated by the tunneling factor for the electron from the delocalized state at the band edge to the defect site within the Wentzel-Kramers-Brillouin (WKB) approximation. As such, Aij is temperature independent. Hence, when studying the temperature dependence of the charge capture and emission processes the line shape function needs to be evaluated. The vibrational wave functions of the two involved defect configurations can overlap not only at but also below the intersection point of the two parabolas, as shown in
| TABLE 2 |
|---|
| Defect parameters of the charge trap causing the RTS signal |
| Defect parameter | Lower limit | Upper limit |
| Relaxation energy Erelax | 0.3 | eV | 1 | eV |
| Configuration coordinate distance ΔQ | 2 Å√u | 2.4 Å√u |
| Trap level ET above Al2O3 EVB | 3.9 | eV | 4 | eV |
| Interface distance d | 1.1 | nm | 1.2 | nm |
[0121]Parameters were extracted based on the modeled line shape function describing the low-temperature vibrational response of the charge transfer.
[0122]Firstly, the distance of more than 1 nm from the interface shows that we are likely dealing with an oxide defect within the Al2O3 gate oxide which causes the observed RTS. The extracted defect level ET is within a range that corresponds to the defect levels of an oxygen vacancy or an aluminum interstitial. The vibronic properties on the other hand (i.e., the small dQ) show that the charge transfer is dominated by nuclear tunneling, leading to the observed temperature independence at low temperatures. In non-glass-forming oxides, like Al2O3 or HfO2, the relaxation energies of point defects are typically on the order of about 1 eV, further confirming the hypothesis an oxygen vacancy or Al interstitial in the ALD-deposited Al2O3 causing the RTS.
Observation of Giant and Anomalous RTS
[0123]
was found to be ˜80%
as a function of VBG. RTS is expected if the number of defects within the device falls into the red shaded area, the single defect limit as shown in
[0124]Giant RTS have been reported in the past for scaled Si FETs as well as carbon nanotube (CNT) FETs. Campbell et. al have observed giant RTS in the sub-threshold operation regime in a scaled n-type Si FET. Their RTS trace revealed
where, ΔIDS corresponds to the difference between the two discrete current levels. Similarly, Asenov et. al have reported
in sub-100 nm Si FETs with dopant atoms. Fantini et. al have investigated the RTS as a function of carrier concentration. Their study revealed that the measured RTS had an amplitude that was an order of magnitude higher than what was predicted by the classical theory of carrier number and correlated mobility fluctuations. Beyond Si FETs, Liu et. al observed giant RTS in ultra-scaled CNT FETs with
as high as 60%.
was found to be ˜80%.
as a function of VBG. Clearly, the RTS strength diminishes as the device is biased from the subthreshold into the on-state.
[0125]In general, it should be noted that the observation of an RTS signal in these large area devices is unusual, even more so in the large step heights. For typical defect densities of 8·1011 cm−2 there should be as many as 20,000 defects within the device area of 2.5 μm2. This approximate number is considerably above the single-defect limit of around 100 defects where one would expect to see charge capture and emission by single defects as RTS for specific bias and temperature conditions, see
[0126]Apart from the normal two-state RTS induced by a single defect having two discrete current levels, more complex RTS with multiple states have been observed in our monolayer MoS2 FETs. These include RTS with three, four, and five discrete current levels. These types of RTS fall under the category of anomalous RTS with varying numbers of metastable states and have been reported in the literature.
[0127]In conclusion, we have studied the dynamics of single defects in a large area grown monolayer MoS2 FET. By changing the temperature and the gate bias we can observe diverse RTS and extract information on the energetics, vibrational properties, and physical location of the defect. In this way, we observed nuclear tunneling at low temperatures and could identify charge trapping at an Al interstitial or O vacancy at about 1.2 nm distance from the interface as a dominant defect candidate. In addition, the observation of RTS signals and large step heights in these large area 2D FETs, indicate that oxide traps in the vicinity to the Schottky barriers at the contacts or close to step edges in the bilayer islands on top of MOCVD-grown monolayer MoS2 could cause current crowding, thereby effectively narrowing down the channel of the devices and increasing the step heights. Using detailed characterization and modeling techniques, we report the observation of RTS in FETs based on large area-grown monolayer MoS2 with ALD-grown Al2O3 as the gate dielectric. We also discuss various characterization approaches utilized in this study for RTS analysis including PSD, TLP, histogram plots, edge detection methods, and non-radiative multiphonon models. Finally, we discuss several types of RTS including giant RTS, multi-state RTS, and anomalous RTS indicating rich defect dynamics in monolayer MoS2 FETs.
Methods
Large-Area Monolayer MoS 2 Film Growth
[0128]Uniform monolayer MoS2 films are grown on 1 cm2 c-plane sapphire substrates (Cryscore Optoelectronic Ltd, 99.996% purity) using a custom-built metal-organic chemical vapor deposition (MOCVD) system. The MOCVD chamber is equipped with a stainless-steel bubbler containing 10 g of Mo(CO)6 (99.99% purity, Sigma-Aldrich) which serves as the Mo precursor source, and a 500 ml H2S (99.5%, Sigma-Aldrich) lecture bottle which provides sulfur during synthesis. Before introducing Mo(CO)6 and H2S, 2 s.l.m. of high-purity argon (Ar) gas, is continuously flown through the chamber, and serves as the main push gas to deliver precursors to the substrate. During film synthesis, chamber temperature and pressure are set to 1000° C. and 50 Torr, respectively. Like prior reports, we employ a multistep growth process comprising nucleation, ripening, and lateral growth stages to better control the nucleation rate on the sapphire substrates. Mo(CO)6 is injected at flow rates of 1.5×10−3 and 7.5×10−4 sccm during the nucleation and lateral growth steps, respectively. H2S flow is maintained at 20 sccm throughout the entire growth process. Complete monolayer coalescence is achieved after 42 minutes of total growth time.
H 2 S Annealing
[0129]H2S annealing is performed ex-situ in the same MOCVD chamber used for MoS2 film synthesis. Monolayer MoS2 samples are placed on alumina crucibles (AdValue Tech, >99.6% purity) placed at the center of the hot zone. The furnace is ramped up to 500° C. (the annealing temperature) at a rate of 50° C./min. 40 sccm of H2S and 2 s.l.m. are continuously flown through the chamber and serve as the S source and push gas, respectively. The annealing process is carried out at a pressure of 50 Torr for a total time of 30 minutes.
Application Substrate Preparation and MoS 2 Film Transfer
[0130]To fabricate the 2D memtransistors, the MOCVD-grown monolayer MoS2 film first had to be transferred from the sapphire growth substrate to the application substrate, which consisted of a global Al2O3/Pt/TiN/p++-Si back-gate stack. The TiN and Pt layers were deposited using reactive sputtering with the underlying Si and a back-gate electrode, respectively. 50 nm of Al2O3 (εox≈10) was grown on the Pt electrode via atomic layer deposition (ALD) to act as the back-gate dielectric. Film transfer was performed using a polymethyl-methacrylate (PMMA)-assisted wet transfer process [63, 64]. First, the as-grown MoS2 on the sapphire substrate was spin-coated with PMMA and baked at 150° C. for 90 s to ensure good PMMA/MoS2 adhesion. The edges of the spin-coated film were then scratched using a razor blade and the substrate was immersed inside a deionized (DI) water bath held at 90° C. for 1 hr. Capillary action caused the water to be preferentially drawn into the substrate/MoS2 interface, owing to the hydrophilic nature of sapphire and hydrophobic nature of MoS2 and PMMA, separating the PMMA/MoS2 stack from the sapphire substrate. The separated film was then fished from the water bath using the application substrate. Subsequently, the substrates were baked at 50° C. and 70° C. for 10 min each to remove moisture and promote film adhesion, thus ensuring pristine interfaces, before the PMMA was removed by immersing the samples in acetone for 12 hrs followed by a 30 min 2-propanol (IPA) clean.
Fabrication of 2D FETs
[0131]To define the channel regions of the MoS2 FETs discussed in this work, the application substrates, with MoS2, transferred on top, were spin-coated with PMMA A6 (4000 RPM for 45 s) and baked at 180° C. for 90 s. The resist was then exposed using electron beam (e-beam) lithography and developed using a 1:1 mixture of 4-methyl-2-pentanone (MIBK) (60 seconds) and IPA (45 seconds). The exposed monolayer MoS2 film was subsequently etched using a sulfur hexafluoride (SF6) reactive ion etching (RIE) at 5° C. for 30 s; Next, the samples were rinsed in acetone and IPA to remove the e-beam resist. To define the source and drain contacts, samples were then spin-coated with a bilayer resist consisting of methyl methacrylate (MMA) and A3 PMMA. E-beam lithography was used to define the source and drain contacts and development was performed using the same 1:1 mixture of MIBK and IPA. E-beam evaporation was used to deposit the contact metals 40/30 nm Ni/Au. Finally, a lift-off process was performed to remove excess resist and metal by immersing the sample in acetone for 1 hr followed by IPA for another 30 mins.
Raman and Photoluminescence (PL) Spectroscopy
[0132]Raman and PL spectroscopy of the pre- and post-irradiation MoS2 film were performed on a Horiba LabRAM HR Evolution confocal Raman microscope with a 532 nm laser. The power was 34 mW filtered at 5% to 1.7 mW. The objective magnification was 100× with a numerical aperture of 0.9, and the grating had a spacing of 1800 gr/mm for Raman and 300 gr/mm for PL.
Electrical Characterization
[0133]Electrical characterization of the fabricated devices was performed in a Lake Shore CRX-VF probe station under atmospheric conditions using a Keysight B1500A parameter analyzer.
NMP Model
[0134]The non-radiative multi-phonon model accounts for the electron-phonon coupling which drives the charge transfer between the atomic defect and the charge reservoir (i.e., conduction band) by modeling the reaction within diabatic potential energy curves in a parabolic approximation close to the minima of the potential energy curves. In a first-order perturbation approach, Fermi's golden rule can be applied to calculate the transition rate for the two states involved, consisting of both electrons, described by the electronic wave functions Φi, Φj, and nuclei states represented by the vibrational states ηi.α, ηi.β,
Here, the Hamiltonian H describes the interaction between the electronic states and the vibrational states, and the transitions occur where the energies of the states of the initial state Eiα and the final state Ejβ are the same. As the electronic states vary only weakly with the nuclei coordinates, the Franck-Condon principle can be applied, and the transition rate can be reformulated as a product of the electronic matrix element Aij and the lineshape function ƒijLSF. While the matrix element describes the likelihood of an electronic transition, the line shape function contains all vibrational interactions caused by the lattice reconfigurations at the defect site. For describing these vibrational interactions, the sum over all modes β weighted by their respective occupation probabilities according to Boltzmann factors need to be formed and averaged over all populated initial states α. The NMP transition rates are the inverse of the experimentally determined capture and emission time constants kC=1/τc=kij and are given by,
with the electronic wave functions Φi, Φj, and the vibrational states ηi.α, ηi.β, describing the nuclei configurations. For more information about the evaluation of these expressions.
[0135]It should be understood that the disclosure of a range of values is a disclosure of every numerical value within that range, including the end points. It should also be appreciated that some components, features, and/or configurations may be described in connection with only one particular embodiment, but these same components, features, and/or configurations can be applied or used with many other embodiments and should be considered applicable to the other embodiments, unless stated otherwise or unless such a component, feature, and/or configuration is technically impossible to use with the other embodiment. Thus, the components, features, and/or configurations of the various embodiments can be combined together in any manner and such combinations are expressly contemplated and disclosed by this statement.
[0136]It will be apparent to those skilled in the art that numerous modifications and variations of the described examples and embodiments are possible considering the above teachings of the disclosure. The disclosed examples and embodiments are presented for purposes of illustration only. Other alternate embodiments may include some or all of the features disclosed herein. Therefore, it is the intent to cover all such modifications and alternate embodiments as may come within the true scope of this invention, which is to be given the full breadth thereof.
[0137]It should be understood that modifications to the embodiments disclosed herein can be made to meet a particular set of design criteria. Therefore, while certain exemplary embodiments of the devices, systems, circuits, and methods of using and making the same disclosed herein have been discussed and illustrated, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.
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Claims
1. (canceled)
2. An s-bit generator, comprising:
a plurality of 2D memtransistors;
an inverting amplifier; and
a programmable threshold inverter;
wherein one or more s-bits are generated from inherent stochasticity in the plurality of 2D memtransistors.
3. The s-bit generator of
the plurality of 2D memtransistors form a voltage divider.
4. The s-bit generator of
the inherent stochasticity in the plural 2D memtransistors includes one or more of: cycle-to-cycle fluctuations in carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor of the plural 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors, and/or random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor of the plural 2D memtransistors.
5. A s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate;
a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and
a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to: the MT3-drain, the MT5-drain, and a node N1;
the MT1-gate is connected to a node N2;
the MT1-source is connected to: the MT2-drain and the MT4-gate via a node N5;
the MT2-drain is connected to the MT4-gate via the node N5;
the MT2-gate is connected to a node N3;
the MT2-source is connected to: the MT4-source, the MT6-source, and a node N4;
the MT3-drain is connected to: the MT1-drain, the MT5-drain, and the node N1;
the MT3-gate is connected to the MT6-gate via a node N6;
the MT3-source is connected to: the MT6-gate via node the N6 and the MT4-drain via the node N6;
the MT4-drain is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT6-gate via the node N6;
the MT4-gate is connected to: the MT1-source via the node N5 and the MT2-drain via the node N5;
the MT4-source is connected to: the MT2-source, the MT6-source, and the node N4;
the MT5-drain is connected to: the MT1-drain, the MT3-drain, and the node N1;
the MT5-gate is connected to the MT6-drain via a node N7;
the MT6-drain is connected to: the MT5-source via the node N7 and the MT5-gate via the node N7;
the MT6-gate is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT4-drain via the node N6; and
the MT6-source is connected to: the MT4-source, the MT2-source, and the node N4.
6. The s-bit generator of
the 2D channel is a monolayer.
7. The s-bit generator of
wherein the monolayer includes MoS2.
8. A stochastic computing processor, comprising:
a processing module including a processor and a memory and the s-bit generator of
9. The stochastic computing processor of
the stochastic computing processor has a non-von Neuman architecture.
10. A stochastic multiplier, comprising:
a first s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate;
a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and
a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to: the MT3-drain, the MT5-drain, and a node N1;
the MT1-gate is connected to a node N2;
the MT1-source is connected to: the MT2-drain and the MT4-gate via a node N5;
the MT2-drain is connected to the MT4-gate via the node N5;
the MT2-gate is connected to a node N3;
the MT2-source is connected to: the MT4-source, the MT6-source, and a node N4;
the MT3-drain is connected to: the MT1-drain, the MT5-drain, and the node N1;
the MT3-gate is connected to the MT6-gate via a node N6;
the MT3-source is connected to: the MT6-gate via the node N6 and the MT4-drain via the node N6;
the MT4-drain is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT6-gate via the node N6;
the MT4-gate is connected to: the MT1-source via the node N5 and the MT2-drain via the node N5;
the MT4-source is connected to: the MT2-source, the MT6-source, and the node N4;
the MT5-drain is connected to: the MT1-drain, the MT3-drain, and the node N1;
the MT5-gate is connected to the MT6-drain via a node N7;
the MT6-drain is connected to: the MT5-source via the node N7 and the MT5-gate via the node N7;
the MT6-gate is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT4-drain via the node N6;
the MT6-source is connected to: the MT4-source, the MT2-source, and the node N4; and
the first s-bit generator is configured to generate an output A at the node N7;
a second s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT14, having a MT14-drain, a MT14-source, and a MT14-gate;
a memtransistor, MT15, having a MT15-drain, a MT15-source, and a MT15-gate;
a memtransistor, MT12, having a MT12-drain, a MT12-source, and a MT12-gate;
a memtransistor, MT13, having a MT13-drain, a MT13-source, and a MT13-gate;
a memtransistor, MT10, having a MT10-drain, a MT10-source, and a MT10-gate; and
a memtransistor, MT1, having a MT11-drain, a MT11-source, and a MT1-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT14-drain is connected to: the MT12-drain, the MT10-drain, and a VDD;
the MT14-gate is connected to a node N12;
the MT14-source is connected to: the MT15-drain and the MT13-gate via a node N11;
the MT15-drain is connected to the MT13-gate via the node N11;
the MT15-gate is connected to a node N13;
the MT15-source is connected to: the MT13-source, the MT11-source, and a GND;
the MT12-drain is connected to: the MT14-drain, the MT10-drain, and a VDD;
the MT12-gate is connected to the MT1-gate via a node N10;
the MT12-source is connected to: the MT1-gate via the node N10 and the MT13-drain via the node N10;
the MT13-drain is connected to: the MT12-source via the node N10, the MT12-gate via the node N10, and the MT1-gate via the node N10;
the MT13-gate is connected to: the MT14-source via the node N11 and the MT15-drain via the node N11;
the MT13-source is connected to: the MT14-source, the MT11-source, and the GND;
the MT10-drain is connected to: the MT14-drain, the MT12-drain, and the VDD;
the MT10-gate is connected to the MT11-drain via a node N9;
the MT11-drain is connected to: the MT10-source via the node N9 and the MT10-gate via the node N9;
the MT1-gate is connected to: the MT12-source via the node N10, the MT12-gate via the node N10, and the MT13-drain via the node N10;
the MT11-source is connected to: the MT13-source, the MT15-source, and the GND; and
the second s-bit generator is configured to generate an output B at the node N9; and
an AND gate configured to receive the output A, receive the output B, and generate an output C.
11. The stochastic multiplier of
the AND gate includes a plurality of memtransistors, comprising:
a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate;
a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate; and
a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate.
12. The stochastic multiplier of
for the first s-bit generator:
the output A is transmitted to the AND gate via the node N7;
the node N7 is connected to the MT7-gate;
the MT1-drain, the MT3-drain, and the MT5-drain are connected to the MT7-drain; and
the MT2-source, the MT4-source, and the MT6-source are connected to: the MT9-gate and to the MT9-source;
for the second s-bit generator:
the output B is transmitted to the AND gate via the node N9;
the node N7 is connected to the MT8-gate;
the MT10-drain, the MT12-drain, and the MT14-drain are connected to the MT7-drain; and
the MT14-source, the MT13-source, and the MT11-source are connected to: the MT9-gate and to the MT9-source;
for the AND gate:
the MT7-source is connected to the MT8-drain;
the MT8-source connected to the MT9-drain and to a node N8; and
the AND gate outputs the output C at the node N8.
13. A stochastic adder, comprising:
a first s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate;
a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and
a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to: the MT3-drain, the MT5-drain, and a node N1;
the MT1-gate is connected to a node N2;
the MT1-source is connected to: MT2-drain and MT4-gate via a node N5;
the MT2-drain is connected to MT4-gate via node the N5;
the MT2-gate is connected to a node N3;
the MT2-source is connected to: the MT4-source, the MT6-source, and a node N4;
the MT3-drain is connected to: the MT1-drain, the MT5-drain, and the node N1;
the MT3-gate is connected to the MT6-gate via a node N6;
the MT3-source is connected to: the MT6-gate via the node N6 and the MT4-drain via the node N6;
the MT4-drain is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT6-gate via the node N6;
the MT4-gate is connected to: the MT1-source via the node N5 and the MT2-drain via the node N5;
the MT4-source is connected to: the MT2-source, the MT6-source, and the node N4;
the MT5-drain is connected to: the MT1-drain, the MT3-drain, and the node N1;
the MT5-gate is connected to the MT6-drain via a node N7;
the MT6-drain is connected to: the MT5-source via the node N7 and the MT5-gate via the node N7;
the MT6-gate is connected to: the MT3-source via the node N6, the MT3-gate via the node N6, and the MT4-drain via the node N6;
the MT6-source is connected to: the MT4-source, the MT2-source, and the node N4; and
the first s-bit generator is configured to generate an output S;
a second s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate;
a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate;
a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate;
a memtransistor, MT10, having a MT10-drain, a MT10-source, and a MT10-gate;
a memtransistor, MT1, having a MT11-drain, a MT11-source, and a MT1-gate; and
a memtransistor, MT12, having a MT12-drain, a MT12-source, and a MT12-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT7-drain is connected to: the MT9-drain, the MT11-drain, and a node VDD;
the MT7-gate is connected to a node N8;
the MT7-source is connected to: the MT8-drain and the MT10-gate via a node N10;
the MT8-drain is connected to the MT10-gate via the node N10;
the MT2-gate is connected to the node N3;
the MT8-source is connected to: the MT10-source, the MT12-source, and a GND;
the MT9-drain is connected to: the MT7-drain, the MT11-drain, and the VDD;
the MT9-gate is connected to the MT12-gate via a node N11;
the MT9-source is connected to: the MT12-gate via the node N11 and the MT10-drain via the node N11;
the MT10-drain is connected to: the MT9-source via the node N11, the MT9-gate via the node N11, and the MT12-gate via the node N11;
the MT10-gate is connected to: the MT7-source via the node N10 and the MT8-drain via the node N10;
the MT10-source is connected to: the MT8-source, the MT12-source, and the GND:
the MT11-drain is connected to: the MT7-drain, the MT9-drain, and the VDD;
the MT1-gate is connected to the MT12-drain via a node N12;
the MT12-drain is connected to: the MT11-source via the node N12 and MT1-gate via the node N12;
MT12-gate is connected to: the MT9-source via the node N11, the MT9-gate via the node N11, and the MT10-drain via the node N11;
the MT12-source is connected to: the MT10-source, the MT8-source, and the GND; and
the second s-bit generator is configured to generate an output A;
a third s-bit generator, comprising:
a plurality of memtransistors, comprising:
a memtransistor, MT13, having a MT13-drain, a MT13-source, and a MT13-gate;
a memtransistor, MT14, having a MT14-drain, a MT14-source, and a MT14-gate;
a memtransistor, MT15, having a MT15-drain, a MT15-source, and a MT15-gate;
a memtransistor, MT16, having a MT16-drain, a MT16-source, and a MT16-gate;
a memtransistor, MT17, having a MT17-drain, a MT17-source, and a MT17-gate; and
a memtransistor, MT18, having a MT18-drain, a MT18-source, and a MT18-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT17-drain is connected to: the MT15-drain, the MT13-drain, and the VDD;
the MT17-gate is connected to a node N16;
the MT17-source is connected to: the MT18-drain and the MT16-gate via a node N15;
the MT18-drain is connected to the MT16-gate via the node N15;
the MT18-gate is connected to a node N17;
the MT18-source is connected to: the MT16-source, the MT14-source, and the GND;
the MT15-drain is connected to: the MT17-drain, the MT13-drain, and the VDD;
the MT15-gate is connected to the MT14-gate via a node N14;
the MT15-source is connected to: the MT14-gate via the node N14 and the MT16-drain via the node N14;
the MT16-drain is connected to: the MT15-source via the node N14, the MT15-gate via the node N14, and the MT14-gate via the node N14;
the MT16-gate is connected to: the MT17-source via the node N15 and the MT18-drain via the node N15;
the MT16-source is connected to: the MT14-source, the MT18-source, and the GND:
the MT13-drain is connected to: the MT17-drain, the MT15-drain, and the VDD;
the MT13-gate is connected to the MT14-drain via a node N13;
the MT14-drain is connected to: the MT13-source via the node N13 and the MT13-gate via the node N13;
the MT14-gate is connected to: the MT15-source via the node N14, the MT15-gate via the node N14, and the MT16-drain via the node N14;
the MT15-source is connected to: the MT16-source, the MT18-source, and the GND; and
the third s-bit generator is configured to generate an output B; and
a MUX gate configured to receive output S, receive the output A, receive the output B, and generate an output C.
14. The stochastic adder of
the MUX gate includes a plurality of memtransistors, comprising:
a memtransistor, MT19, having a MT19-drain, a MT19-source, and a MT19-gate;
a memtransistor, MT20, having a MT20-drain, a MT20-source, and a MT20-gate;
a memtransistor, MT21, having a MT21-drain, a MT21-source, and a MT21-gate; and
a memtransistor, MT22, having a MT22-drain, a MT22-source, and a MT22-gate.
15. The stochastic adder of
for the first s-bit generator:
the node N1 is connected to the VDD;
the node N7 is connected to the MT20-gate; and
the node N4 is connected to the GND;
for the second s-bit generator:
the MT7-drain, the MT9-drain, and the MT11-drain are connected to the MT19-drain; and
the node N12 is connected to the MT21-drain;
for the third s-bit generator:
the node N13 is connected to the MT22-source;
for the MUX gate:
the MT19-drain is connected to the node N1 and the VDD;
the MT19-gate is connected to: the MT21-gate via the node N18 and the MT20-drain via the node N18;
the MT19-source is connected to: the MT21-gate via the node N18 and the MT20-drain via the node N18;
the MT20-drain is connected to: the MT19-gate via the node N18, the MT19-source via the node N18, and the MT21-gate via the node N18;
the MT20-gate is connected to: the node N7 and the MT22-gate;
the MT20-source is connected to the node N4 and the GND;
the MT21-drain is connected to the node N12;
the MT21-gate is connected to: the MT19-source via the node N18, the MT19-gate via the node N18, and the MT20-drain via the node N18;
the MT21-source is connected to the MT22-drain via the node N19;
the MT22-drain is connected to the MT21-source via the node N19;
the MT22-gate is connected to the MT20-gate;
the MT22-source is connected to the node N13; and
the MUX gate outputs the output C at the node N19.
16. A stochastic subtractor, comprising:
a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B, wherein the output A and the output B are correlated bit streams;
an XOR gate, comprising a plurality of memtransistors including:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate;
a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate;
a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate;
a memtransistor, MT7, having a MT7-drain, a MT7-source, and a MT7-gate; and
a memtransistor, MT8, having a MT8-drain, a MT8-source, and a MT8-gate;
a memtransistor, MT9, having a MT9-drain, a MT9-source, and a MT9-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to: a node N1, the MT3-drain, the MT5-drain, the MT7-drain, and a VDD;
the MT1-gate is connected to: the MT7-gate and the MT2-drain via a node N2;
the MT1-source is connected to the MT2-drain via the node N2;
the MT2-drain is connected to: the MT1-source via the node N2 and the MT1-gate via the node N2;
the MT2-gate is connected to the MT4-gate via the node N4;
the MT2-source is connected to: the MT9-gate via a node N3 and a GND;
the MT3-drain is connected to: the node N1, the MT1-drain, the MT5-drain, the MT7-drain, and the VDD;
the MT3-gate is connected to: the MT5-gate and the MT6-drain via a node N6;
the MT3-source is connected to the MT4-drain;
the MT4-drain is connected to the MT3-source;
the MT4-gate is connected to the MT2-gate via a node N4;
the MT4-source is connected to: the MT9-drain via a node N5 and the MT8-source via the node N5;
the MT5-drain is connected to: the node N1, the MT1-drain, the MT3-drain, the MT7-drain, and the VDD;
the MT5-gate is connected to: the MT3-gate and the MT6-drain via the node N6;
the MT5-source is connected to: the MT3-gate via the node N6 and the MT6-drain via the node N6;
the MT6-drain is connected to: the MT5-source via the node N6, the MT5-gate via the node N6, and the MT3-gate via the node N6;
the MT6-gate is connected to: the MT8-gate via the node N7;
the MT6-source is connected to: a node N8 and the GND;
the MT7-drain is connected to: the node N1, the MT1-drain, the MT3-drain, the MT5-drain, and the VDD;
the MT7-gate is connected to: the MT1-gate, the MT1-source, and the MT2-drain via the node N2;
the MT7-source is connected to the MT8-drain;
the MT8-drain is connected to the MT7-source;
the MT8-gate is connected to the MT6-gate via the node N7;
the MT8-source is connected to the MT9-drain via the node N5;
the MT9-drain is connected to the MT4-source via the node N5 and the MT8-source via the node N5;
the MT9-gate is connected to: the node N3 and the GND;
the MT9-source is connected to: the node N3 and the GND;
the output A is received at the node N4 and the output B is received at the node N7;
the MT1 and the MT2, together, act as a NOT gate to invert the output A to generate output Ac;
the MT5 and the MT6, together, act as a NOT gate to invert the output B to generate Bc; and
the XOR gate is configured to receive the output A, receive the output B, and generate an output C via the node N5.
17. A stochastic correlator, comprising:
a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B, wherein the output A and the output B are uncorrelated bit streams;
an OR gate, comprising a plurality of memtransistors including:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to: a node N1 and a VDD;
the MT1-gate is connected to a node N2;
the MT1-source is connected to: the MT2-source, a node N4, and the MT3-drain;
the MT2-drain is connected to: the node N1 and the VDD;
the MT2-gate is connected to a node N3;
the MT2-drain is connected to: the MT1-source, the node N4, and the MT3-drain;
the MT3-drain is connected to the MT1-source, the MT2-source, and the node N4;
the MT3-gate is connected to the node N5 and the GND;
the MT3-source is connected to the GND; and
the OR gate is configured to receive the output A at the node N2, receive the output B at the node N3, and generate an output C via the node N4.
18. A stochastic sorter, comprising:
a first s-bit generator configured to generate output A, and a second s-bit generator configured to generate output B;
an OR gate configured to receive the output A, receive the output B, and generate an output C that is a maximum value of the output A and the output B; and
an AND gate configured to receive the output A, receive the output B, and generate an output D that is a minimum value of the output A and the output B.
19. The stochastic sorter of
the OR gate and the AND gate include a plurality of memtransistors including:
a memtransistor, MT1, having a MT1-drain, a MT1-source, and a MT1-gate;
a memtransistor, MT2, having a MT2-drain, a MT2-source, and a MT2-gate;
a memtransistor, MT3, having a MT3-drain, a MT3-source, and a MT3-gate;
a memtransistor, MT4, having a MT4-drain, a MT4-source, and a MT4-gate;
a memtransistor, MT5, having a MT5-drain, a MT5-source, and a MT5-gate; and
a memtransistor, MT6, having a MT6-drain, a MT6-source, and a MT6-gate;
wherein:
each memtransistor is stacked on a non-volatile and programmable local back-gate stack;
each memtransistor has a 2D channel formed between its source and its drain;
the MT1-drain is connected to a node N1 and a VDD;
the MT1-gate is connected to the MT5-gate via a node N2 and a node N3;
the MT1-source is connected to the MT2-drain;
the MT2-drain is connected to the MT1-source;
the MT2-gate is connected to the MT4-gate via the node N3;
the MT2-source is connected to the MT3-drain via a node N4;
the MT3-drain is connected to the MT2-source via the node N4;
the MT3-gate is connected to: a GND and the MT3-source via a node N5;
the MT3-source is connected to: the GND via the node N5 and the MT3-gate via the node N5;
the MT4-drain is connected to: the node N1, the VDD via the node N1, and the MT5-drain via the node N1;
the MT4-gate is connected to the MT2-gate via the node N3;
the MT4-source is connected to: the MT5-source, a node N6, and the MT6-drain;
the MT5-drain is connected to: the node N1, the VDD, and the MT4-drain via the Node N1;
the MT5-gate is connected to the MT1-gate via the node N2;
the MT5-source is connected to: the MT4-source, the node N6, and the MT6-drain;
the MT6-drain is connected to the node N6, the MT5-source, and the MT4-source;
the MT6-gate is connected to the node N5 and the GND via the node N5;
the MT6-source is connected to the GND and the node N5;
the output A from the first s-bit generator is received at the node N3, the output B from the second s-bit generator is received at the node N2, the output C is generated at the node N6, and the output D is generated at the node N4.