Company patents

Absolics Inc.

Absolics Inc. demonstrates a strong and rapidly evolving focus on core semiconductor technologies, with Semiconductor Packaging & Encapsulation accounting for 58.4% of its portfolio and Semiconductor Manufacturing Process for 35.1%, both showing explosive growth in 2025 (92.3% and 375.0% YoY respectively). While patenting activity in these core areas, and others like Multi-Chip & 3D Assemblies and Chip-to-Chip Interconnect, has seen a sharp decline so far in 2026, emerging interests in Coating & Surface Treatment and Glass & Glass-Ceramics (each with 2 patents so far in 2026 after minimal prior activity) suggest a potential diversification or refinement of their material science approach within the semiconductor domain.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

77 US filings (since 2023) · 11 categories · 14 themes

Advanced Electronic Packaging

Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.

Printed Circuits & Electronic Assemblies
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45since 2023
+170.0%YoY
Electronics Encapsulation & Sealing

Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.

Semiconductor Packaging & Encapsulation
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8since 2023
+200.0%YoY
Fan-Out & Embedded Die Packaging

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Semiconductor Packaging & EncapsulationMulti-Chip & 3D AssembliesChip-to-Chip Interconnect (Bonding, Bumps)
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7since 2023
+50.0%YoY
Wafer Handling and Process Environment Control

Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.

Semiconductor Manufacturing Process
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6since 2023
-33.3%YoY
Encapsulation Materials & Processes

Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.

Semiconductor Packaging & Encapsulation
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4since 2023
0.0%YoY
Glass Surface Functionalization

Application of coatings, layers, or chemical treatments to the surface of glass articles to impart specific functionalities such as UV blocking, anti-whitening, hydrophobicity, or adhesion for subsequent layers.

Glass & Glass-Ceramics
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3since 2023
+300.0%YoY
Thin & Flexible Glass Substrates

Manufacturing and processing techniques for producing ultra-thin glass articles, often with enhanced flexibility and mechanical properties, suitable for use as substrates in electronic displays, foldable devices, or other advanced electronics.

Glass & Glass-Ceramics
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3since 2023
+300.0%YoY
Package Thermal Management

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Semiconductor Packaging & EncapsulationChip-to-Chip Interconnect (Bonding, Bumps)
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2since 2023
n/a
Specialized End-Effectors & Mechanisms

Design and control of advanced robotic grippers, tools, and mechanical linkages for specific manipulation tasks or operating in challenging environments.

Manipulators & Robotics
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1since 2023
new
3D Die Stacking & Vertical Interconnects

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Semiconductor Packaging & Encapsulation
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1since 2023
n/a
Advanced Package Interconnects

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Semiconductor Packaging & Encapsulation
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1since 2023
n/a
Temporary Wafer Bonding & Debonding

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Semiconductor Manufacturing Process
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1since 2023
n/a
Chemically Strengthened Glass

Glass articles treated with ion exchange or other chemical processes to induce a surface compressive stress layer, enhancing mechanical strength, scratch resistance, and impact toughness.

Glass & Glass-Ceramics
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1since 2023
n/a
Precision Substrate and Wafer Cleaning

Specialized cleaning techniques and apparatus designed for removing microscopic contaminants, residues, or films from sensitive substrates, such as semiconductor wafers or flat panel displays, often involving chemical, mechanical, or plasma-based methods.

Cleaning Processes
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1since 2023
n/a

Patents

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