UnfoldIPThemes

Company patents

Adeia Semiconductor Inc.

Adeia Semiconductor Inc. demonstrates a strong and consistent focus on core semiconductor packaging and interconnect technologies, with Chip-to-Chip Interconnect (Bonding, Bumps) (70.7% of portfolio) and Semiconductor Packaging & Encapsulation (68.3% of portfolio) showing significant growth in 2025 at +44.4% and +62.5% YoY, respectively. While patenting activity across most categories shows a sharp decline so far in 2026, the sustained growth in these areas through 2025 suggests a strategic emphasis on advanced packaging solutions, with Multi-Chip & 3D Assemblies also seeing a remarkable +175.0% YoY growth in 2024.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

41 US filings (since 2023) · 12 categories · 5 themes

3D Die Stacking & Vertical Interconnects

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Chip-to-Chip Interconnect (Bonding, Bumps)Semiconductor Packaging & EncapsulationMulti-Chip & 3D AssembliesSemiconductor Diodes & TransistorsMemory Devices (Structural)
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30since 2023
+55.6%YoY
Integrated Circuit Interconnect & Layout Optimization

Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.

Integrated Circuit Layout & Arrangement
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23since 2023
0.0%YoY
Advanced Memory Cell Structures

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Memory Devices (Structural)
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15since 2023
+16.7%YoY
Heterogeneous Chiplet Integration

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Multi-Chip & 3D Assemblies
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14since 2023
-16.7%YoY
Backside Contact & Interconnectsfiltered

Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.

Transistor & Device Structure
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4since 2023
new

Patents

Showing 1-4 of 4

Backside Contact & Interconnects
Page 1 of 1
US 20250204006 A1APPLICATION
H10D64/23

TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCONNECTS

Filed:2025-03-06Pub:2025-06-19
Applicant:Adeia Semiconductor Inc.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

US 12272730 B2GRANTED
H01L29/66

Transistor level interconnection methodologies utilizing 3D interconnects

Filed:2022-12-28Pub:2025-04-08
Applicant:Adeia Semiconductor Inc.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

US 11688776 B2GRANTED
H01L21/76

Transistor level interconnection methodologies utilizing 3D interconnects

Filed:2021-03-30Pub:2023-06-27
Applicant:ADEIA SEMICONDUCTOR INC.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

US 20230138732 A1APPLICATION
H01L29/417

TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCONNECTS

Filed:2022-12-28Pub:2023-05-04
Applicant:Adeia Semiconductor Inc.

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

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