ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through the system board.

Disclosed are architectures of semiconductor integrated circuit (IC) device, more specifically an artificial intelligence (AI) accelerator. The AI accelerator comprises a processing block, a memory block disposed laterally side-by-side to each other and over a common substrate, and a logic base die vertically interposed between the common substrate and the memory block. The processing block comprises a computing die that comprises a plurality of parallel processing cores for processing artificial intelligence algorithms. The memory block heterogeneously integrated with the processing block through electrical connections formed in the common substrate. The memory block comprises a memory stack that comprises one or more vertically stacked memory die layers. The logic base die comprises one or more data communication interfaces between the memory block and the processing block. The data communication interfaces include at least a network on chip configured to electrically connect the memory block with each processing core.

A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

Disclosed are system and methods of dynamically balancing power and performance of a processing unit. The method includes receiving workloads to be processed by the processing unit; classifying, using a recurrent neural network, the workloads according to expected resources to be expended by different functional blocks; identifying a critical path workload based on the classification of workloads; determining a temperature-independent operating frequency for the critical path workload; determining a temperature-dependent operating frequency for the critical path workload based on a junction temperature of the processing unit; adjusting the temperature-dependent operating frequency to a target operating frequency having a value within a predetermined difference from the temperature-independent operating frequency by actively cooling the processing unit; setting a critical path supply voltage based on the target operating frequency; and setting a non-critical path voltage for remaining ones of the workloads at a value less than the critical path supply voltage.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

Disclosed are architectures of semiconductor integrated circuit (IC) device. The semiconductor IC device includes a unified logic die and a memory array die heterogeneously integrated with the unified logic die. The unified logic die includes a compute logic block and a memory the memory logic block monolithically integrated with the compute logic block die on a same substrate. The memory logic block includes a memory peripheral circuitry configured for controlling a memory cell array external to the unified logic die. The memory array die includes the memory cell array, and the memory array die is communicatively coupled with the memory logic block.