Advanced Semiconductor Engineering Inc

A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

Package structures and methods of manufacturing a package structure are disclosed. The method includes providing a carrier, wherein the carrier comprises an alignment mark; and attaching a mold chase to a first region of the carrier, wherein the alignment mark is outside the first region.

A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.

The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.

An electronic device is provided. The electronic device includes a first photonic component, a memory module, and a plurality of processing units. The memory module includes a plurality of memory components supported by the first photonic component. The processing units are distributed at a periphery of the memory module, wherein the memory module is configured to be accessed by at least two of the processing units through the first photonic component.

A bonding structure is provided. The bonding structure includes a lower pad and an upper pad. The lower pad includes a first nanotwin copper (NT-Cu) structure including a [111] crystallographic plane. The lower pad also includes a first non-NT-Cu structure encapsulating the first NT-Cu structure. The upper pad is bonded to the lower pad.

A package structure is provided. The package structure includes a first substrate, a first dielectric layer, and a first conductive element. The first dielectric layer is over the first substrate and has an opening defined by a sloped sidewall. The first conductive element is in the opening and has an upper surface. The first conductive element includes a first portion over the sloped sidewall and a second portion distinct from the first portion. The first portion and the second portion include a plurality of first nanotwinned layers and second nanotwinned layers stacked substantially along different respective directions defining an angle of greater than 0° and less than 90°. The upper surface includes two surface portions each being an upper surface of the first portion and an upper surface of the second portion of the first conductive element, and the two surface portions have different widths in a cross-sectional view.

The present disclosure provides a power module. The power module includes a first circuit structure, a second circuit structure, and a first power element. The second circuit structure is over the first circuit structure. The first power element is disposed between the first circuit structure and the second circuit structure. The first power element is configured to transmit a power passing through the first power element and the first circuit structure.

A circuit structure is provided. The circuit structure includes a first circuit layer and a second circuit layer. The first circuit layer includes a first nanotwin copper (NT-Cu) structure and a first non-NT-Cu structure. The second circuit layer is over the first circuit layer. The second circuit layer includes a second NT-Cu structure and a second non-NT-Cu structure. The first NT-Cu structure vertically overlaps the second NT-Cu structure.

The present disclosure provides an electronic device, which includes a circuit structure, a processing component, a first storage unit, and a second storage unit. The processing component is disposed over the circuit structure. The first storage unit is supported by the circuit structure, and electrically connected to the processing component. The second storage unit is disposed under the circuit structure and electrically connected to the processing component via the circuit structure.