ADVANTEST CORPORATION

An interface device is provided between a test head and a device under test (DUT). A front-end module includes a pin electronics circuit and a flexible printed circuit (FPC) cable. An interposer is placed on the FPC cable and forms a contact surface with the socket board. A frame is assembled to the front-end module. The frame has a reference surface and the reference surface being brought into contact with the contact surface when the frame is assembled to the front-end module. The socket board is assembled to the frame.

The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

There is provided a variable attenuator including: a transmission line which has an open stub that is connected between an input and an output of the variable attenuator; a first switch which is connected between the input and a reference potential; and a second switch which is connected between the output and the reference potential.

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.

An interface device is provided between a test head and a device under test (DUT). A socket board includes sockets each configured to mount a DUT, and a socket PCB having a first face that mounts the sockets and a second face provided with multiple back face electrodes. An interposer has a first face provided with multiple deformable electrodes and a second face provided with multiple non-deformable electrodes and is configured such that the multiple deformable electrodes are in contact with the multiple back face electrodes of the socket PCB. An FPC cable has multiple electrode pads to be coupled with the multiple non-deformable electrodes on the second face of the first interposer.

Provided is a testing apparatus including: a light emission control unit which causes a plurality of light emitting elements to be tested to emit light; a light measurement unit which receives the light emitted from the plurality of light emitting elements and measures wavelengths of the received light; and a determination unit which determines whether there is an abnormality in at least one light emitting element on the basis of intensity distributions of the wavelengths of the light, which is emitted from the plurality of light emitting elements, measured by the light measurement unit. The testing apparatus may further include: a light source; an optical system which irradiates the plurality of light emitting elements with light emitted from the light source; and an electrical measurement unit which measures a photoelectric signal obtained by each of the plurality of light emitting elements photoelectrically converting the light radiated by the optical system.

An electromagnetic wave measuring apparatus irradiates an irradiation target having a measuring target with a pre-irradiation electromagnetic wave and, based on a post-irradiation electromagnetic wave obtained, measures the measuring target. The post-irradiation electromagnetic wave has a response component from the measuring target and a background component corresponding to the pre-irradiation electromagnetic wave. The electromagnetic wave measuring apparatus includes a first frequency spectrum acquiring section, a second frequency spectrum acquiring section, and a subtracting section. The first frequency spectrum acquiring section acquires a frequency spectrum of a first signal that includes the background component and the response component of the post-irradiation electromagnetic wave. The second frequency spectrum acquiring section acquires a frequency spectrum of a second signal that includes the background component of the post-irradiation electromagnetic wave. The subtracting section subtracts the frequency spectrum of the second signal from the frequency spectrum of the first signal.

Embodiments of the present invention provide a test system that includes an integrated protocol analyzer (IPA) and wherein memory allocated to different DUTs can be pooled for improved capture depth during testing. The IPA also monitors one or more sideband communication channels (or for system events) and can advantageously trigger a response by the test system (e.g., the capturing and/or filtering of data) during device testing based on prescribed sideband data or prescribed system events. The sideband channel can also be used to transmit commands and signals generated by a sideband automatic pattern generator (APG) of an FPGA in communication with a DUT to test or configure the DUT. The sideband channel can be monitored continuously to identify signals, commands, or other data that trigger certain responses by the FPGA or other test system components. The sidebands are typically implemented using dedicated input/output pins of the DUT and the FPGA.

Methods and systems for determining whether a measurement system is used in a valid state, includes: automatically reading out a plurality of information items; automatically obtaining information on current operating environmental conditions; automatically reading reference information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components and information on reference operating environmental conditions; and comparing the read out information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components with the reference information items identifying the measurement system components and/or representing one or more characteristics of the measurement system components, and checking whether the current operating environmental conditions comprise an allowable value or are within an allowable range defined by the information on the reference operating environmental conditions, in order to determine whether the measurement system comprising the plurality of measurement system components is used in the valid state.

Provided is a pattern-generating device including: a timing-generating unit which generates a clock signal; a data-generating unit which generates multi-bit data used for generating a multi-level signal having three or more levels; and a control unit which controls the data-generating unit to generate the data, wherein the control unit outputs, based on the clock signal, a trigger signal which triggers the data-generating unit to generate the data, and the data-generating unit outputs, in response to the trigger signal, the multi-bit data for at least one of a rising edge or a falling edge of the clock signal.