Advantest Test Solutions, Inc.

An apparatus for use in testing an integrated circuit semiconductor wafer device under test (wafer DUT) includes a probe configured to probe a surface of the wafer DUT during testing thereof, a thermal interposer (TI) including a heater layer arranged with a plurality of zones corresponding to a plurality of areas of the wafer DUT, the TI configured to come into proximity to a surface of the wafer DUT and further configured to selectively heat the plurality of areas by selectively heating the plurality of zones, the heater layer including a plurality of heating elements configured to correspond to the plurality of zones, and a plurality of temperature measurement devices configured to correspond to the plurality of zones, a cold plate disposed in proximity to the TI and configured to selectively cool the plurality of areas of the wafer DUT, and a thermal controller configured to control selective cooling of the cold plate and configured to control selective heating of the plurality of heating elements of the TI during the testing.

A system for testing circuits of an integrated circuit semiconductor wafer includes a thermal interposer (TI) device for use in testing circuits of a semiconductor device. The TI device includes a top surface configured to receive the semiconductor device, a heating layer defining a plurality of independently controllable thermal zones configured to maintain or change temperatures of the top surface during the testing, a power input configured to receive electrical power and wherein the electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones, and an electromagnetic interference (EMI) shield layer defining the top surface and disposed to shield the top surface from EMI from the heating layer.

A system for testing circuits of an integrated circuit semiconductor wafer includes a test stack for use in testing circuits of an integrated circuit component includes a top surface configured to receive the component in proximity thereto, a plurality of independently controllable thermal zones including a plurality of independently controllable heating zones and a plurality of independently controllable cooling zones configured to maintain or change temperatures on the top surface, and a power input configured to receive electrical power and wherein the electrical power is configured to be selectively applied to one or more of the plurality of independently controllable heating zones.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

Placing a first side of an active thermal interposer device of a thermal management head against a device under test (DUT). Disposing a cold plate against a second side of the active thermal interposer. The DUT includes a die and the active thermal interposer device includes a plurality of zones, each zone of the plurality of zones corresponding to a respective module of the plurality of modules and operable to be selectively heated. Receiving a respective set of inputs corresponding to each zone of the plurality of zones. Performing thermal management of the plurality of modules of the DUT by separately controlling temperature of each zone of the plurality of zones by controlling a supply of coolant to the cold plate, and individually controlling heating of each zone of the plurality of zones.

Embodiments of the present invention provide testing systems that perform advanced system level testing of multiple devices in parallel over a network connection that provides access to multiple development stations for improved efficiency and access to system level testing. A rack integrated computer (RIC) is coupled to multiple tester racks of single board computers (SBCs) and provides access to the SBCs as development workstations for use over a computer network (e.g., a customer network). SBCs can provide end level testing of devices like smartphones that include several different devices (DUTs). Access to the SBCs as development workstations can be enforced on an IP level under a development license, and the license may be used from any global location using a static IP address and/or virtual private network, for example.