Company patents
ALTERA CORPORATION
Altera Corporation's patent strategy reveals a strong, recent surge in core computing and semiconductor technologies, with categories like Pulse / Digital Logic Circuits experiencing a remarkable +218.2% YoY growth in 2025 and Electronic Design Automation (CAD/EDA) growing +400.0% YoY in both 2024 and 2025. While 2026 data is partial, showing a decline across most categories, the substantial growth in 2025 across key areas like Computer Hardware Architecture (+125.0% YoY) and Operating Systems & Program Control (+320.0% YoY) suggests a recent, aggressive push to bolster its intellectual property in these foundational domains.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
235 US filings (since 2023) · 12 categories · 30 themes
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Automated methods and tools for generating, optimizing, and verifying the physical layout and interconnections of electronic components, including integrated circuits, printed circuit boards, and system-level interface protection.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.
Development of encoding and decoding algorithms and apparatuses for robust data transmission and storage, focusing on techniques like LDPC, polar codes, and iterative decoding methods to minimize bit errors and improve communication reliability.
Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.
Methods and architectures for processing digital signals to enhance quality, remove noise, manage group delay, and facilitate symbol decision, often involving digital filters and equalization techniques.
Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.
Techniques for encoding digital data onto analog carrier signals using complex constellation diagrams, multi-level signaling, or layered approaches, often combined with error correction codes, to achieve higher data rates, improved spectral efficiency, or extended range.
Enhancements to the physical and data link layers of network communication, focusing on hardware components, signal integrity, power efficiency, and efficient data transfer mechanisms for specific interfaces and buses.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.
Techniques and circuits designed to detect, estimate, and mitigate various physical layer signal impairments such as frequency spurs, phase noise, or non-linear distortions, thereby improving overall signal quality and system performance.
Focuses on the architectural and circuit-level innovations for Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to improve speed, accuracy, linearity, and power efficiency. Includes specific types like SAR and Delta-Sigma, and their constituent components.
Technologies enabling the creation and management of virtual computing environments, including virtual machines and virtual desktops, with an emphasis on secure and efficient remote access, updates, and performance.
Technologies for deploying, managing, and governing applications and services in cloud environments, particularly focusing on containerization, microservice architectures, API gateways, and distributed data management.
Techniques and systems for optimizing network traffic flow, distributing loads across multiple paths or resources, and ensuring quality of service based on various criteria like application type, latency, or resource availability. This includes dynamic path selection, congestion control, and resource allocation.
Using computational design and simulation to optimize the performance characteristics of specific components or materials within a larger engineering system.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Engineering solutions for creating electronic devices with bendable, foldable, or stretchable form factors, often involving hinges, flexible displays, and sliding mechanisms to enable dynamic physical configurations.
Techniques enabling simultaneous transmission and reception of signals on the same or adjacent frequency bands, including methods for managing and mitigating self-interference and configuring network resources for such operation.
Methods for designing, transmitting, and utilizing specific reference signals (e.g., DMRS, SRS, PT-RS) to enable accurate channel estimation, interference measurement, synchronization, or sensing in wireless communication systems.
Creating virtual models (digital twins) of complex physical systems to simulate their behavior, predict performance, validate designs, or guide operations under various conditions.
Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.
Patents
Showing 1-10 of 292