Company patents
AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Amkor Technology Singapore Holding Pte Ltd. exhibits a highly concentrated patent strategy, with Semiconductor Packaging & Encapsulation representing 87.1% of its total portfolio, and Semiconductor Manufacturing Process, Chip-to-Chip Interconnect (Bonding, Bumps), and Multi-Chip & 3D Assemblies also being major focuses. While patenting in core semiconductor areas saw significant growth in 2024 (e.g., Multi-Chip & 3D Assemblies grew by 150.0% YoY), the company also surprisingly showed an emerging focus in Computer Vision, which experienced a 250.0% YoY growth in 2024, despite a subsequent decline in 2025 and no patents so far in 2026, indicating a potential shift in this exploratory area.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
404 US filings (since 2023) · 11 categories · 18 themes
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Methods and structures for mass-producing and assembling arrays of micro-LEDs onto a substrate, including transfer processes, bonding techniques, and defect management.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.
Design and manufacturing techniques for incorporating antenna structures directly into electronic devices, product housings, or materials, often under constraints of space, aesthetics, or environmental factors.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Techniques and structures used to reduce unwanted electromagnetic coupling, scattering, or interference between multiple antennas, different frequency bands, or sensitive electronic components within a device.
Focuses on advanced pixel architectures, often involving vertical stacking (3D) or silicon-on-insulator (SOI) structures, to improve performance, density, or functionality of photodiodes, transistors, and floating diffusion regions within image sensor pixels.
Systems and methods for electronically steering or shaping antenna beams by controlling the phase and amplitude of signals fed to individual elements in an array, including calibration techniques and multi-antenna configurations.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Patents
Showing 1-10 of 634