Company patents

Amlogic (Shanghai) Co., Ltd.

Amlogic (Shanghai) Co., Ltd. shows a surprising shift in its patent strategy, moving away from its traditional strength in Pictorial / Video Communications, which saw a significant decline of 60.0% so far in 2026, and a sharp decrease in Image Processing (YoY -80.0% in 2024). Concurrently, the company is rapidly emerging in Wireless Networks, with an impressive 400.0% year-over-year growth in 2026, and also showing new focus in Computer Hardware Architecture and System Reliability & Diagnostics, each with 3 patents so far in 2026 after little to no activity in prior years.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

40 US filings (since 2023) · 12 categories · 13 themes

Video Quality & Encoding Optimizationfiltered

Methods and apparatus for improving the visual fidelity, resolution, or compression efficiency of video signals, often through advanced processing, up-scaling, or neural network-based filters.

Pictorial / Video CommunicationsComputer Vision
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16since 2023
+500.0%YoY
Video Enhancement & Object Tracking

Methods and systems for improving the quality of video streams, generating intermediate frames, or continuously locating and following objects within a sequence of images, even under occlusion.

Image Processing
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13since 2023
+100.0%YoY
Advanced Image Processing for Displays

Algorithms and hardware implementations within display drivers or associated components to enhance visual quality, resolution, or color reproduction, including upscaling, dithering, and compensation for display artifacts like crosstalk.

Display Drivers
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12since 2023
+300.0%YoY
Efficient Visual Feature Extraction

Algorithms and hardware optimizations for rapidly identifying and characterizing relevant visual features (e.g., objects, motion, gradients) from images or video streams, often integrating machine learning for feature representation and recognition, with a focus on real-time performance and reduced computational cost.

Pattern Recognition & ML Models
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5since 2023
new
Advanced RF & Beam Management

Techniques and hardware architectures for optimizing the radio frequency (RF) front-end, antenna systems, and beamforming strategies in wireless networks to improve signal quality, capacity, and interference mitigation.

Wireless Networks
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3since 2023
new
High-Speed Clock & Data

Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.

Pulse / Digital Logic Circuits
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3since 2023
new
Memory System Performance & Reliability

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Computer Hardware Architecture
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2since 2023
new
Display Power Management

Techniques and circuits for optimizing power consumption, voltage stability, and energy efficiency in display panels, often involving dynamic voltage scaling, duty cycle control, or remnant voltage management.

Display Drivers
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2since 2023
new
High-Speed Data Interconnects

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Computer Hardware Architecture
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1since 2023
new
Vision-Based Object & Pose Estimation

Methods and apparatus for detecting objects and determining their three-dimensional position and orientation (pose) using imagery or point cloud data, often for navigation, surveying, or environmental understanding.

Computer Vision
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1since 2023
new
Device Enclosure & Material Engineering

Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.

Printed Circuits & Electronic Assemblies
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1since 2023
new
Advanced Electronic Packaging

Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.

Printed Circuits & Electronic Assemblies
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1since 2023
new
Advanced Modulation & Coding Schemes

Techniques for encoding digital data onto analog carrier signals using complex constellation diagrams, multi-level signaling, or layered approaches, often combined with error correction codes, to achieve higher data rates, improved spectral efficiency, or extended range.

Physical Transmission & Modulation
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1since 2023
n/a

Patents

Page 1 of 4
US 20250168374 A1APPLICATION
H04N19/423

MEMORY STRUCTURE, STORAGE METHOD, ENTROPY DECODING METHOD, CHIP, DEVICE, AND STORAGE MEDIUM

Filed:2024-11-15Pub:2025-05-22
Applicant:Amlogic (Shanghai) Co., Ltd.

Disclosed are a memory structure, a storage method, an entropy decoding method, a chip, a device, and a storage medium. The memory structure includes: a row storage circuit including a plurality of row storage components in a number identical to a number of rows of a decoding unit, where the row storage components correspond one-to-one to ordinates of the decoding unit, and each row storage component is configured to store a coding coefficient under a corresponding ordinate, and an abscissa of the coding coefficient; a column storage circuit including a plurality of column storage components in a number identical to a number of columns of the decoding unit, where the column storage components correspond one-to-one to abscissas of the decoding unit, and each column storage component is configured to store a coding coefficient under a corresponding abscissa, and an ordinate of the stored coding coefficient; and diagonal storage components in a number equaling 1 subtracted from the sum of the number of rows and the number of columns of the decoding unit, where each diagonal storage component is configured to store a coding coefficient on a corresponding diagonal position line, and an abscissa or an ordinate of the stored coding coefficient. According to the disclosure, an occupied area of the memory structure is reduced.