Ampere Computing LLC

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

A system and method are provided that enable a processor to have the immutable code and data that it uses for its boot process to be securely patched. A system may include a read only memory (ROM) storing one or more certificates and instructions, an array of one-time programmable (OTP) indicators, a bootstrap controller connected to the ROM and the array of OTP indicators, and a random access memory (RAM) connected to the bootstrap controller. The bootstrap controller is configured to verify integrity of firmware for boot based on certificates stored in ROM, check for a patch in the array of OTP indicators, and write the one or more certificates and the instructions in ROM and the patch into the RAM. The patch may be loaded into RAM by the bootstrap controller and overwrite ROM instructions or certificates in RAM.

A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.

Aspects of the disclosure relate generally to the design of the functional units of a processor core, and more specifically, to adding logical operations of a first functional unit of a processor core to a second functional unit of the processor core. In an aspect, a processor core includes a first functional unit configured to provide first functionality, wherein the first functional unit includes circuitry configured to perform a first set of logical operations, a second functional unit configured to provide second functionality different from the first functionality, wherein the second functional unit includes circuitry configured to perform a subset of logical operations of the first set of logical operations, and a data bus connecting the first functional unit and the second functional unit.

Disclosed is a branch predictor unit (BPU), comprising a first branch predictor configured to generate a first prediction of a branch based at least in part on a first prediction entry point of two predictions prior to the first prediction, and a second branch predictor configured to generate a second prediction of the branch based at least in part on a second prediction entry point of one prediction prior to the second prediction, wherein either the first prediction or the second prediction is generated based on a determination of whether the branch follows a flush.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

Disclosed are techniques for performing a gather operation using one register file entry as the destination for all of the load suboperations. In an aspect, a method of performing a gather operation using one register file entry comprises detecting a gather operation comprising a plurality of load suboperations accessing independent, possibly disjoint memory locations, performing the plurality of load suboperations, wherein each load suboperation writes to a different portion of the one register file entry without overwriting the other portions of the one register file entry. The method further includes determining that all of the plurality of load suboperations have been completed, and upon determining that all of the plurality of load suboperations have been completed, making the one register file entry available for a read operation.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

Disclosed is a branch predictor unit (BPU), comprising a loop predictor configured to predict a repeatedly looping behavior before the repeatedly looping behavior occurs, a loop detector configured to detect the repeatedly looping behavior which is currently occurring, and a loop buffer, configured to treat a plurality of looping operations corresponding to the repeatedly looping behavior as a read-only circular buffer without removing the looping operations from the loop buffer.

Disclosed is a prefetcher, e.g., of a system with one or more cores. The prefetcher determines data dependency access (DDA) patterns, such as array indirect access, and prefetches data based on the DDA patterns. The training for the DDA patterns may take place upon an occurrence of a prefetch training reset event. The prefetch training reset event may be an execution level change or a context switch.