Company patents

Arm Limited

Arm Limited's patent strategy reveals a surprising shift away from core computing areas, with significant year-over-year declines in patent filings across nearly all categories so far in 2026, including a -40.8% drop in Computer Hardware Architecture (27.6% of portfolio) and a -46.2% decline in Operating Systems & Program Control (27.1% of portfolio). While Image Processing saw rapid growth of +66.0% in 2024 and +21.8% in 2025, and Input/Output & User Interfaces grew by +73.9% in 2024, these emerging focuses also show substantial declines so far in 2026, suggesting a broader re-evaluation of R&D priorities.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

1,715 US filings (since 2023) · 12 categories · 37 themes

Real-time Graphics Rendering is up +28.6% YoY. Worth a look.
Memory System Performance & Reliability

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Computer Hardware ArchitectureMemory & Storage (Static)
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516since 2023
-0.6%YoY
Specialized Compute Architectures

Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.

Computer Hardware Architecture
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507since 2023
+10.8%YoY
Real-time Graphics Rendering

Techniques and hardware architectures designed to efficiently generate and display complex 3D graphics, particularly for interactive applications like virtual reality, focusing on speed and visual quality.

Image Processing
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177since 2023
+28.6%YoY
Memory Reliability, Testing & Repairfiltered

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.

Memory & Storage (Static)
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176since 2023
+1.9%YoY
AI/ML Hardware Acceleration

Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.

Machine Learning & AIComputer Hardware ArchitectureHardware Platform (Cooling, Power, Packaging)
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161since 2023
-23.5%YoY
High-Speed Clock & Data

Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.

Pulse / Digital Logic Circuits
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139since 2023
+23.7%YoY
Video Quality & Encoding Optimization

Methods and apparatus for improving the visual fidelity, resolution, or compression efficiency of video signals, often through advanced processing, up-scaling, or neural network-based filters.

Computer VisionPictorial / Video Communications
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112since 2023
+80.8%YoY
Advanced Memory Cell Structures

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Memory & Storage (Static)
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79since 2023
-35.7%YoY
In-Memory Sensing & Data Path

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Memory & Storage (Static)
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52since 2023
-6.2%YoY
System Resource & Power Optimization

Methods and systems for efficiently allocating computing resources, balancing workloads, and managing power states to improve performance, reduce energy consumption, or enhance reliability in computing platforms.

Operating Systems & Program Control
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42since 2023
+157.1%YoY
Video Enhancement & Object Tracking

Methods and systems for improving the quality of video streams, generating intermediate frames, or continuously locating and following objects within a sequence of images, even under occlusion.

Image Processing
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40since 2023
+44.4%YoY
Specialized Neural Network Architectures

Development and optimization of novel neural network layers or architectures specifically designed to improve performance or efficiency for computer vision tasks.

Computer Vision
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38since 2023
-42.9%YoY
High-Speed Data Interconnects

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Computer Hardware Architecture
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36since 2023
-10.0%YoY
Predictive System Health

Techniques for monitoring system components and behaviors to anticipate failures, performance degradation, or anomalies, often leveraging machine learning for pattern recognition and forecasting.

System Reliability & Diagnostics
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35since 2023
+87.5%YoY
Power Delivery & Battery Management

Techniques for efficiently supplying power to electronic devices, managing battery charge/discharge cycles, optimizing power consumption, and converting power between different voltage levels or AC/DC for improved energy efficiency and longevity.

Hardware Platform (Cooling, Power, Packaging)
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25since 2023
+100.0%YoY
Secure Data Storage & Provenance

Techniques for protecting data at rest or in backup, ensuring its integrity, confidentiality, and verifiable origin, often involving encryption, unique identifiers, or secure repositories.

Computer Security
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24since 2023
-60.0%YoY
On-Chip Power Management & Protection

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Computer Hardware Architecture
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22since 2023
+133.3%YoY
AR/VR User Interfaces

Techniques for rendering, interacting with, and managing content within augmented or virtual reality environments, including spatial tracking, gaze interaction, and dynamic multi-application display management.

Input/Output & User Interfaces
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15since 2023
-50.0%YoY
Analog Sensing Interfaces

Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.

Pulse / Digital Logic Circuits
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14since 2023
-40.0%YoY
Power Switching & Drivers

Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.

Pulse / Digital Logic Circuits
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14since 2023
0.0%YoY
Secure Data Sharing & Rights Management

Mechanisms to facilitate the secure exchange of data between different entities or systems while enforcing usage policies, managing digital content rights, and ensuring data consistency during replication or transfer.

Computer Security
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13since 2023
-42.9%YoY
Wearable & Mobile Interaction

Designing user interfaces and interaction methods specifically for mobile or wearable devices, enabling control of external systems, monitoring user states, or facilitating real-world transactions.

Input/Output & User Interfaces
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13since 2023
-25.0%YoY
AI/ML for Cryptographic Security

Applying artificial intelligence and machine learning techniques to enhance cryptographic systems, such as generating encryption models, improving zero-trust architectures, or enabling privacy-preserving computations like federated learning.

Computer Security
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11since 2023
-75.0%YoY
Interactive & Generative Display Systems

Technologies that create dynamic and interactive visual content for displays, including virtual/wearable systems, by generating overlays, replacing input streams, or merging real-time user actions with digital environments.

Pictorial / Video Communications
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10since 2023
-50.0%YoY
Virtualization & Secure Remote Access

Technologies enabling the creation and management of virtual computing environments, including virtual machines and virtual desktops, with an emphasis on secure and efficient remote access, updates, and performance.

Operating Systems & Program Control
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9since 2023
+50.0%YoY
Access Control & Identity Management

Systems and methods for authenticating users, devices, or applications, authorizing their access to resources based on policies, and managing digital identities across various platforms.

Computer Security
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9since 2023
0.0%YoY
Compliance & Transaction Validation

Systems and methods designed to ensure adherence to regulatory rules, corporate policies, or contractual agreements, often involving automated validation of electronic transactions, smart contract enforcement, or API governance.

Operating Systems & Program Control
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6since 2023
+100.0%YoY
Vision-Based Object & Pose Estimation

Methods and apparatus for detecting objects and determining their three-dimensional position and orientation (pose) using imagery or point cloud data, often for navigation, surveying, or environmental understanding.

Computer Vision
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6since 2023
0.0%YoY
Quantum Control Circuits

Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.

Pulse / Digital Logic Circuits
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4since 2023
0.0%YoY
MLOps & Model Deployment

Systems and methods for automating the lifecycle of machine learning models, including pipeline deployment, model management, versioning, and configuring for different inference environments.

Machine Learning & AI
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3since 2023
+300.0%YoY
Automated Visual Inspection

Systems that employ imaging and image processing to automatically detect defects, verify states, or ensure quality control in manufactured goods, printed materials, or industrial processes.

Pictorial / Video Communications
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3since 2023
new
Automated Fault Response

Involves systems designed to automatically detect errors or failures and initiate predefined or intelligent corrective actions, recovery procedures, or notifications to minimize downtime and manual intervention.

System Reliability & Diagnostics
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3since 2023
0.0%YoY
Sensor-based Environment Perception

Techniques and hardware for autonomous systems to gather and interpret data about their surroundings, including obstacle detection, object recognition, and depth estimation, to inform control decisions.

Computer Vision
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3since 2023
0.0%YoY
Quantum Machine Learning

Developing and applying machine learning algorithms that leverage quantum computing principles, such as quantum circuits or autoencoders, for tasks like simulation or data processing.

Machine Learning & AI
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2since 2023
new
AI for Medical Diagnostics

Utilizing machine learning, particularly deep learning, to analyze medical data such as images, sensor readings, or physiological signals for disease prediction, diagnosis, or treatment assessment.

Image ProcessingComputer Vision
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1since 2023
new
Federated & Distributed ML

Methods for training machine learning models across multiple decentralized devices or servers while keeping data localized, often involving aggregation of model parameters and secure communication.

Machine Learning & AI
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1since 2023
n/a
Flexible/Foldable Device Structures

Engineering solutions for creating electronic devices with bendable, foldable, or stretchable form factors, often involving hinges, flexible displays, and sliding mechanisms to enable dynamic physical configurations.

Hardware Platform (Cooling, Power, Packaging)
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1since 2023
n/a

Patents

Page 29 of 30
US 20210035653 A1APPLICATION
G11C29/38

APPARATUS AND METHOD

Filed:2019-07-31Pub:2021-02-04
Applicant:Arm Limited

Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to detect a fault condition when the result of the check operation performed by the memory error protection circuitry is inconsistent with the difference between the first test memory address and the second test memory address.

US 10910082 B1GRANTED
G11C29/38

Apparatus and method

Filed:2019-07-31Pub:2021-02-02
Applicant:Arm Limited

Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to detect a fault condition when the result of the check operation performed by the memory error protection circuitry is inconsistent with the difference between the first test memory address and the second test memory address.