Arm Limited

A circuit includes first and second logic gates, where the first logic gate is configured to output a bitline precharge signal based on a global bitline precharge signal and an output of the second logic gate, and the output of the second logic gate is based on at least a sense amplifier precharge signal and a control signal. Also, the circuit is configured to control a precharge of one or more bitcells based on enabling or disabling the bitline precharge signal. A method includes: detecting, by a circuit, one GTP pulse or two GTP pulses per unit cycle, where the one GTP pulse corresponds to either a read operation or a write operation, and the two GTP pulses correspond to both the read operation and the write operation.

There is provided an apparatus comprising first processing circuitry operating in a first clock domain having a first clock signal operating at a first clock period. The apparatus is provided with timeout period generation circuitry to couple with a second clock domain to generate a timeout clock signal, the second clock domain comprising second processing circuitry and having a second clock signal operating at a second clock period. The apparatus is provided with control circuitry to compare first data generated by the first processing circuitry against second data received from the second processing circuitry. The control circuitry is configured to indicate when the first and second data do not match within a timeout period. The timeout period generation circuitry is configured to receive second clock information indicative of the second clock period and to generate the timeout clock signal based on the second clock information and the first clock period.

A clock throttler circuit for droop mitigation and disclose circuitry, related methods and state machine, the method performed at a system to select a first clock signal or a second clock signal to be provided to a subsystem, the method including: receiving, from a droop detector, a trigger signal indicative of a droop event at the subsystem; invoking modulation circuitry to throttle the selectable clock signal in accordance with the event; selecting the first clock signal; providing, to the modulation circuitry, the first clock signal to be throttled.

A throttler based mitigator including circuitry, related methods and state machine, the circuitry including: a first component to: receive a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit; determine a current index implemented at the clock throttle circuit, where the current index corresponds to a current level of throttle of the clock output signal; provide, responsive to the determination, an index signal to cause the clock throttle circuit to throttle the clock output signal in accordance with the index signal.

Clock throttler architecture including clock throttler circuitry, related methods and state machine, where the clock throttler circuitry includes: first selection circuitry to select a first pattern of a plurality of patterns in storage, where each pattern of the plurality of patterns comprises a plurality of bits; second selection circuitry to sequentially select bits of the first pattern and to provide the selected bits to clock gate circuitry in a successive manner; where the clock gate circuitry is to receive a clock input signal and to pass or gate pulses of the clock input signal responsive to applying the selected bits to generate a clock output signal.

An order controlling interconnect circuit node of a data processing system couples to an interconnect circuit of a network and to target nodes. The node includes transmitting interface circuitry, message receiving interface circuitry, and control circuitry. The control circuitry is configured to monitor incoming “ready” response messages at the message receiving circuitry and to control the message transmitting interface circuity to send a cancellation request message to the target node of the oldest write request of the one or more second write-push requests when a “ready” response message has not been received for the first write-push request within a designated time period. Subsequent to sending the cancellation request message, a continuation request message is to the target node of the oldest write-push request of the one or more second write-push requests when a “ready” response message has been received for the first write-push request.

There is described delay circuitry including: a pulse generator to generate a pulse responsive to receiving an input signal edge and to buffer and invert the input signal edge; and a signal output element to receive the pulse and the buffered and inverted signal edge from the pulse generator and to generate a delayed signal edge responsive to a trailing edge of the pulse and based on the buffered and inverted signal edge. In addition, there is described delay circuitry including: a buffer-inverter unit to receive, buffer and invert an input signal and to generate a delayed output signal, the buffer-inverter unit including a signal-controlled gate to invert the input signal arranged in series with a mode-controlled gate to pass the input signal. Finally, there is described apparatus including the delay circuitry and a flip flop.

There is provided an apparatus comprising bridge circuitry to couple processing circuitry to an allocated subset of a plurality of port controllers for connecting the processing circuitry to link partners. The bridge circuitry is configured to perform a data transfer between the processing circuitry and the allocated subset according to a bandwidth quota. The apparatus is provided with control circuitry to receive configuration information identifying the allocated subset, and to allocate a bandwidth share to each port controller identified in the allocated subset. The control circuitry is configured to determine the bandwidth share based on the configuration information. The control circuitry is configured, for each given port controller identified in the allocated subset, to implement a restriction to limit the data transfer between the given port controller and the processing circuitry according to the bandwidth share allocated to the given port controller.

An apparatus has decoding circuitry to decode instructions defined according to an instruction set architecture (ISA) support a loop control instruction providing an explicit loop presence hint indicating that a sequence of instructions to be executed includes a program loop body to be iterated. Processing circuitry performs data processing in response to the decoded instructions. Prefetch circuitry generates a prefetch request for data to be prefetched into a cache corresponding to an address predicted to be accessed by the processing circuitry in future. In response to determining that the decoding circuitry has detected the loop control instruction, the prefetch circuitry activates generation of at least one loop-control-instruction-triggered stream of prefetch requests specifying addresses predicted based on a property of at least one instruction of the program loop body whose presence is indicated by the loop control instruction.

A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.