Company patents

Arm Limited

Arm Limited's patent strategy reveals a surprising shift, with its core Computer Hardware Architecture and Operating Systems & Program Control categories, representing 27.7% and 27.0% of its portfolio respectively, showing significant declines in patent filings in 2026 so far (YoY -36.7% and -42.8%). While Machine Learning & AI has seen consistent year-over-year declines since 2023, an emerging focus is evident in Pulse / Digital Logic Circuits, which grew by 62.5% in 2025 and is up 15.4% so far in 2026, suggesting a strategic pivot towards foundational semiconductor technologies.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

1,764 US filings (since 2023) · 12 categories · 37 themes

Real-time Graphics Rendering is up +28.6% YoY. Worth a look.
Memory System Performance & Reliability

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Computer Hardware ArchitectureMemory & Storage (Static)
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533since 2023
-0.6%YoY
Specialized Compute Architectures

Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.

Computer Hardware Architecture
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520since 2023
+10.8%YoY
Memory Reliability, Testing & Repair

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.

Memory & Storage (Static)
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184since 2023
+1.9%YoY
Real-time Graphics Rendering

Techniques and hardware architectures designed to efficiently generate and display complex 3D graphics, particularly for interactive applications like virtual reality, focusing on speed and visual quality.

Image Processing
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182since 2023
+28.6%YoY
AI/ML Hardware Acceleration

Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.

Machine Learning & AIComputer Hardware ArchitectureHardware Platform (Cooling, Power, Packaging)
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167since 2023
-23.5%YoY
High-Speed Clock & Data

Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.

Pulse / Digital Logic Circuits
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141since 2023
+23.7%YoY
Video Quality & Encoding Optimization

Methods and apparatus for improving the visual fidelity, resolution, or compression efficiency of video signals, often through advanced processing, up-scaling, or neural network-based filters.

Computer VisionPictorial / Video Communications
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118since 2023
+80.8%YoY
Advanced Memory Cell Structures

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Memory & Storage (Static)
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82since 2023
-35.7%YoY
In-Memory Sensing & Data Path

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Memory & Storage (Static)
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54since 2023
-6.2%YoY
System Resource & Power Optimization

Methods and systems for efficiently allocating computing resources, balancing workloads, and managing power states to improve performance, reduce energy consumption, or enhance reliability in computing platforms.

Operating Systems & Program Control
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43since 2023
+157.1%YoY
Video Enhancement & Object Tracking

Methods and systems for improving the quality of video streams, generating intermediate frames, or continuously locating and following objects within a sequence of images, even under occlusion.

Image Processing
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42since 2023
+44.4%YoY
Specialized Neural Network Architectures

Development and optimization of novel neural network layers or architectures specifically designed to improve performance or efficiency for computer vision tasks.

Computer Vision
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40since 2023
-42.9%YoY
High-Speed Data Interconnects

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Computer Hardware Architecture
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37since 2023
-10.0%YoY
Predictive System Health

Techniques for monitoring system components and behaviors to anticipate failures, performance degradation, or anomalies, often leveraging machine learning for pattern recognition and forecasting.

System Reliability & Diagnostics
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35since 2023
+87.5%YoY
Power Delivery & Battery Management

Techniques for efficiently supplying power to electronic devices, managing battery charge/discharge cycles, optimizing power consumption, and converting power between different voltage levels or AC/DC for improved energy efficiency and longevity.

Hardware Platform (Cooling, Power, Packaging)
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25since 2023
+100.0%YoY
Secure Data Storage & Provenance

Techniques for protecting data at rest or in backup, ensuring its integrity, confidentiality, and verifiable origin, often involving encryption, unique identifiers, or secure repositories.

Computer Security
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24since 2023
-60.0%YoY
On-Chip Power Management & Protection

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Computer Hardware Architecture
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22since 2023
+133.3%YoY
AR/VR User Interfaces

Techniques for rendering, interacting with, and managing content within augmented or virtual reality environments, including spatial tracking, gaze interaction, and dynamic multi-application display management.

Input/Output & User Interfaces
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16since 2023
-50.0%YoY
Secure Data Sharing & Rights Management

Mechanisms to facilitate the secure exchange of data between different entities or systems while enforcing usage policies, managing digital content rights, and ensuring data consistency during replication or transfer.

Computer Security
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14since 2023
-42.9%YoY
Analog Sensing Interfaces

Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.

Pulse / Digital Logic Circuits
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14since 2023
-40.0%YoY
Power Switching & Drivers

Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.

Pulse / Digital Logic Circuits
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14since 2023
0.0%YoY
Wearable & Mobile Interaction

Designing user interfaces and interaction methods specifically for mobile or wearable devices, enabling control of external systems, monitoring user states, or facilitating real-world transactions.

Input/Output & User Interfaces
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13since 2023
-25.0%YoY
AI/ML for Cryptographic Security

Applying artificial intelligence and machine learning techniques to enhance cryptographic systems, such as generating encryption models, improving zero-trust architectures, or enabling privacy-preserving computations like federated learning.

Computer Security
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11since 2023
-75.0%YoY
Interactive & Generative Display Systems

Technologies that create dynamic and interactive visual content for displays, including virtual/wearable systems, by generating overlays, replacing input streams, or merging real-time user actions with digital environments.

Pictorial / Video Communications
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10since 2023
-50.0%YoY
Virtualization & Secure Remote Access

Technologies enabling the creation and management of virtual computing environments, including virtual machines and virtual desktops, with an emphasis on secure and efficient remote access, updates, and performance.

Operating Systems & Program Control
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9since 2023
+50.0%YoY
Access Control & Identity Management

Systems and methods for authenticating users, devices, or applications, authorizing their access to resources based on policies, and managing digital identities across various platforms.

Computer Security
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9since 2023
0.0%YoY
Compliance & Transaction Validation

Systems and methods designed to ensure adherence to regulatory rules, corporate policies, or contractual agreements, often involving automated validation of electronic transactions, smart contract enforcement, or API governance.

Operating Systems & Program Control
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6since 2023
+100.0%YoY
Vision-Based Object & Pose Estimation

Methods and apparatus for detecting objects and determining their three-dimensional position and orientation (pose) using imagery or point cloud data, often for navigation, surveying, or environmental understanding.

Computer Vision
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6since 2023
0.0%YoY
Quantum Control Circuits

Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.

Pulse / Digital Logic Circuits
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4since 2023
0.0%YoY
MLOps & Model Deployment

Systems and methods for automating the lifecycle of machine learning models, including pipeline deployment, model management, versioning, and configuring for different inference environments.

Machine Learning & AI
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3since 2023
+300.0%YoY
Automated Visual Inspection

Systems that employ imaging and image processing to automatically detect defects, verify states, or ensure quality control in manufactured goods, printed materials, or industrial processes.

Pictorial / Video Communications
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3since 2023
new
Automated Fault Response

Involves systems designed to automatically detect errors or failures and initiate predefined or intelligent corrective actions, recovery procedures, or notifications to minimize downtime and manual intervention.

System Reliability & Diagnostics
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3since 2023
0.0%YoY
Sensor-based Environment Perception

Techniques and hardware for autonomous systems to gather and interpret data about their surroundings, including obstacle detection, object recognition, and depth estimation, to inform control decisions.

Computer Vision
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3since 2023
0.0%YoY
Quantum Machine Learning

Developing and applying machine learning algorithms that leverage quantum computing principles, such as quantum circuits or autoencoders, for tasks like simulation or data processing.

Machine Learning & AI
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2since 2023
new
AI for Medical Diagnostics

Utilizing machine learning, particularly deep learning, to analyze medical data such as images, sensor readings, or physiological signals for disease prediction, diagnosis, or treatment assessment.

Image ProcessingComputer Vision
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1since 2023
new
Federated & Distributed ML

Methods for training machine learning models across multiple decentralized devices or servers while keeping data localized, often involving aggregation of model parameters and secure communication.

Machine Learning & AI
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1since 2023
n/a
Flexible/Foldable Device Structures

Engineering solutions for creating electronic devices with bendable, foldable, or stretchable form factors, often involving hinges, flexible displays, and sliding mechanisms to enable dynamic physical configurations.

Hardware Platform (Cooling, Power, Packaging)
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1since 2023
n/a

Patents

Showing 6241-6250 of 6297

Page 625 of 630
US 20110093557 A1APPLICATION
G06F15/16

Maintaining required ordering of transaction requests in interconnects using barriers and hazard checks

Filed:2010-10-13Pub:2011-04-21
Applicant:Peter Andrew Riocreux

Interconnect circuitry for a data processing apparatus with a hazard checker for eliminating barrier transaction requests is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device The interconnect circuitry comprises: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests that occur before the barrier transaction request in the stream of transaction requests with respect to at least some of the transaction requests that occur after the barrier transaction request in the stream of transaction requests. The interconnect circuitry comprises hazard checking circuitry for checking a stream of transaction requests and comparing a transaction request within the stream of transaction requests against earlier outstanding transaction requests that have not yet completed, to determine if the transaction request may potentially generate a data hazard, and in response to detecting a potential hazard between the transaction request and at least one of the outstanding transaction requests the hazard checking circuitry is configured to stall the transaction request until the at least one outstanding transaction request has completed; and barrier termination circuitry associated with the hazard checking circuitry for detecting a barrier transaction request within the stream of transaction requests and terminating the barrier transaction request.

US 20110087819 A1APPLICATION
G06F13/14

Barrier transactions in interconnects

Filed:2010-10-05Pub:2011-04-14
Applicant:Peter Andrew Riocreux

Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.

US 20110087809 A1APPLICATION
G06F13/10

Reduced latency barrier transaction requests in interconnects

Filed:2010-10-05Pub:2011-04-14
Applicant:Peter Andrew Riocreux

Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further.

US 20110085391 A1APPLICATION
G11C7/10

Memory with improved read stability

Filed:2009-11-09Pub:2011-04-14
Applicant:Vikas Chandra

A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device and the reset device to provide the connections; wherein: the data control circuitry is configured to: generate a data access control signal to trigger the access device to provide the connection between the first access node and the at least one data line in response to a write request to write a predetermined value to the storage cell, and in response to a read request to read a stored value from the storage cell; and generate a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.