ASPEED Technology Inc.

A texture prefetching apparatus in a graphics processing system having a texture memory is disclosed, comprising a first FIFO memory, a second FIFO memory, a main rasterizer, an auxiliary rasterizer and a cache data memory. The cache data memory is coupled between the first FIFO memory and the texture memory. The main rasterizer converts destination coordinates of a first pixel in a primitive into a cache entry and a tag for a first integer texel according to texture coordinates and destination coordinates of multiple vertices of the primitive. The auxiliary rasterizer coupled to the second FIFO memory converts destination coordinates of N second pixels in the primitive into multiple cache entries, multiple tags and multiple memory addresses for multiple second integer texels according to the texture coordinates and the destination coordinates of the multiple vertices, where N is a multiple of 4.

A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.

A texture prefetching apparatus in a graphics processing system having a texture memory is disclosed, comprising a first FIFO memory, a second FIFO memory, a main rasterizer, an auxiliary rasterizer and a cache data memory. The cache data memory is coupled between the first FIFO memory and the texture memory. The main rasterizer converts destination coordinates of a first pixel in a primitive into a cache entry and a tag for a first integer texel according to texture coordinates and destination coordinates of multiple vertices of the primitive. The auxiliary rasterizer coupled to the second FIFO memory converts destination coordinates of N second pixels in the primitive into multiple cache entries, multiple tags and multiple memory addresses for multiple second integer texels according to the texture coordinates and the destination coordinates of the multiple vertices, where N is a multiple of 4.

A baseboard management control device is provided. The baseboard management control device includes an input and output device and a baseboard management controller. The input and output device includes a sensing device. The sensing device is coupled to multiple input pins and multiple output pins to sense and write the target data, respectively. The baseboard management controller includes a storage device and a main processor. The storage device is configured to pre-store the target data. The main processor is coupled to the storage device and reads the target data in the storage device according to a predetermined cycle. The baseboard management controller and the input and output device are respectively located on different circuit boards.

Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

A baseboard management control device is provided. The baseboard management control device includes an input and output device and a baseboard management controller. The input and output device includes a sensing device. The sensing device is coupled to multiple input pins and multiple output pins to sense and write the target data, respectively. The baseboard management controller includes a storage device and a main processor. The storage device is configured to pre-store the target data. The main processor is coupled to the storage device and reads the target data in the storage device according to a predetermined cycle. The baseboard management controller and the input and output device are respectively located on different circuit boards.

A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.