ATI TECHNOLOGIES ULC

Embodiments herein describe relaxation oscillator circuits for physical unclonable function (PUF) circuits and/or for providing clocks to multiple dies. The relaxation oscillator circuit generates a clock having a frequency that is based in part on random process variations of the passive components of the relaxation oscillator circuit. The relaxation oscillator circuit may be distributed amongst multiple dies of an integrated circuit device, to incorporate additional sources of randomness/entropy, enhance security, to provide clocks to the multiple dies. The relaxation oscillator circuits include differential and single-ended relaxation oscillator circuits. Resistive and/or capacitive components may be configurable, which may be useful for testing purposes, altering PUF codes, and/or generating time-multiplexed clocks.

A display system includes a rendering device and a display device having a plurality of individually-controllable illumination regions. The rendering device is to render a frame for display at the display device during a frame period and to determine a brightness representation for each region of a plurality of regions of the frame, each region of the frame corresponding to an illumination region of the display device. The rendering device further is to set, for each illumination region, an illumination configuration to be applied by the display device for the illumination region during at least one of the frame period and a subsequent frame period based on the brightness representation for the corresponding region of the frame, wherein the illumination configuration controls at least one of an illumination level, a duration, and a position of an illumination strobe to be implemented for the corresponding illumination region.

Data for nodes of a bounding volume hierarchy can be represented in fixed-point format for compression. For good precision, fixed-point bounds are stored along with each node, where these bounds represent the minimum and maximum representable numbers in the format. While this provides good compression, there are ways in which this technique can produce undesirable results. For example, if the size of many or most of the bounding volumes in the fixed-point number space is significantly smaller than the bounds, then the representation of such bounding volume in the fixed-point space may be unnecessarily large, resulting in a large number of false positive intersections during BVH traversal. Thus, techniques are provided herein for setting certain bounding volumes as “always hit” in order to eliminate the bounding volumes from inclusion in the fixed-point bounds. This shrinks the fixed-point bounds, giving better precision for smaller bounding volumes.

Embodiments herein identify anchor points in an isometric image (e.g., bottom, left, right, and top anchor points) which can be used to adjust the image so it has a desired perspective (e.g., where the angles between the x, y, and z axes are the same). To do so, a system determines horizontal adjustments for the anchor points using polynomial interpolation. The system then determines vertical adjustments for the anchor points using cubic polynomial interpolation. Doing so adjusts or stretches the image so that it has the desired orientation. In this manner, isometric images (e.g., AI-generated images) that each have a different orientation can be separately adjusted to have the same orientation so they, for example, each can be placed in grids with the same dimensions for an isometric game.

A technique for generating backward optical flow data includes identifying a forward velocity value of a picture element at first coordinates in a subsequent frame buffer that stores forward velocity values for a subsequent frame. The technique identifies second coordinates in a previous frame buffer that stores backward velocity values of a previous frame by adjusting the first coordinates based on a negated version of the forward velocity value. A backward velocity value for the picture element at the second coordinates in the previous frame buffer is set to the negated version of the forward velocity value of the picture element at the first coordinates in the subsequent frame buffer. An image is rendered in accordance with the backward velocity value for the picture element at the second coordinates in the previous frame buffer.

A power manager of an apparatus exposes an application programming interface (API) usable for applications to specify priority and quality-of-service (QoS) parameters (e.g., bandwidth requirements) for a workload. An application, for instance, specifies the priority and QoS parameters for a workload to be processed using a hardware compute unit. The power manager employs the priority and QoS parameters to configure the bandwidth allocation to access a memory system. In particular, the bandwidth allocation and prioritization are dynamically extended to real-time and best-effort workloads to satisfy specified QoS parameters for inference workloads and improve user experiences.

An accelerator unit (AU) includes a compute unit configured to execute a first workgroup of a first kernel and a set of compute unit resources allocated to the first workgroup. Concurrently with the compute unit executing the first workgroup, a scheduling circuitry of the AU receives a resource termination hint indicating that the first workgroup is going to end the use of portions of compute unit resources allocated to the first workgroup. In response to this resource termination hint, the scheduling circuitry provisionally allocates these portions of compute unit resources to a second workgroup of a second kernel and begins execution of a portion of the second workgroup. After the first workgroup releases the portions of compute unit resources, the scheduling circuitry fully allocates the portions of compute unit resources to the second workgroup and executes a remainer of the second workgroup.

An apparatus and method for efficiently scheduling instructions for a parallel data processing circuit. In various implementations, a computing system includes a variety of types of processing circuits with two or more capable of executing a same type of task. A hardware component, such as a processing circuit, accesses a command buffer. The processing circuit reads, in the command buffer, a predicate command corresponding to the next task to execute. The processing circuit checks the predicate memory location corresponding to the next task to verify whether another hardware component has started the next task. If any other hardware component has begun executing the task, then the processing circuit discards the task from its command buffer. Otherwise, if no other hardware component has begun executing the task, then the processing circuit updates the predicate memory location corresponding to the task to specify the task has begun execution.

Dynamically modifying voltage regulator modes based on a computing system workload is described. System management circuitry assesses activity and energy demands of a computing system’s hardware components for a given workload and adapts voltage regulator configuration settings to ensure that the voltage regulator is operating in a mode that is optimized for the workload. In some implementations, modifying voltage regulator configuration settings causes a voltage regulator to transition from a current mode to a different mode. Alternatively or additionally, modifying configuration settings causes the voltage regulator to continue operating in a current mode with a different rate of voltage mitigation.

At least one memory is configured to store information representing a distribution of probabilities that a first agent passes through locations in an environment as the first agent moves from a first location to a second location. At least one processor is configured to select a first keypoint in an environment based on the distribution of probabilities and select one or more second keypoints in the environment based on the distribution of probabilities, the first keypoint, and any previously selected keypoints. The at least one processor is also configured to instruct a second agent to move from the first location to the second location along a trajectory that includes the first keypoint and the second keypoint(s). The at least one processor can implement autoregressive generator circuitry and keypoint scheduler circuitry.