ATOMERA INCORPORATED

A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective conductive contact liners in the trenches.

A method for making a semiconductor device may include forming spaced apart shallow trench isolation (STI) regions in a semiconductor layer, etching first portions of the semiconductor layer between adjacent ones of the STI regions to an etch depth, and performing a well implant in the first portions of the semiconductor layer. The method may further include forming respective superlattices on the first portions of the semiconductor layer between the adjacent ones of STI regions and with a height not greater than the etch depth. The method may also include forming respective spaced apart source and drain regions associated with each superlattice, and forming a respective gate above each superlattice.

A method for making a semiconductor device may include implanting non-semiconductor atoms into a localized region of a semiconductor layer, and forming a superlattice on the semiconductor layer over the localized region. The superlattice may include a stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one monolayer of the non-semiconductor atoms constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing a thermal treatment to cause non-semiconductor atoms from the superlattice to be displaced, and to cause non-semiconductor atoms from the localized region to migrate into the superlattice and replace at least some of the displaced non-semiconductor atoms.

A bit line is pre-charged to ground. First and second nodes of a latch are coupled to ground and a reference voltage, respectively. A DRAM bitcell is activated, thereby coupling a DRAM cell capacitor to the bit line, and developing a read voltage on the bit line. The bit line is isolated from the latch when the DRAM bitcell is activated. The first node is decoupled from ground, and the bit line is then coupled to the first node, thereby developing the read voltage on the first node. Then, the second node is de-coupled from the reference voltage, and the bit line is isolated from the first node. The latch is activated, amplifying the voltage difference between the first and second nodes, resulting in a read data voltage on the first node. The bit line is recoupled to the first node, applying the read data voltage to the bit line.

A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, with the third reference voltage being greater than the high logic voltage of the DRAM cell.

A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18 O greater than 10 percent.

A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.

A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.