Beijing ESWIN Computing Technology Co., Ltd.

A method for processing an instruction, a processor, an electronic apparatus and a storage medium are provided. The method for processing the instruction includes: writing an instruction stream into an instruction data cache and a branch prediction error determination unit in parallel in an instruction processing pipeline, and determining a branch instruction in the instruction stream and whether a branch prediction error exists for the branch instruction in the branch prediction error determination unit; and in response to the branch prediction error existing for the branch instruction, performing a flush operation on an object instruction in the instruction processing pipeline that is fetched due to the branch prediction error.

The embodiment of the disclosure provides an electronic device, which includes a functional circuit portion, an electrostatic protection circuit portion, and an external circuit portion. The electrostatic protection circuit portion is configured to electrically connect the functional circuit portion and the external circuit portion to transmit electrical signals, and provide electrostatic protection to the external circuit portion. The external circuit portion includes at least one external terminal and an external control circuit portion that is electrically connected to the external terminal, and the external control circuit portion is configured to control whether the electrical signal is transmitted to the external terminal. The electrostatic protection circuit portion is configured to use the external control circuit portion for electrostatic discharge.

A panel driving circuit includes a detection circuit, a control circuit, and an output circuit. The detection circuit outputs a first detection signal when a data change amount of a drive signal output through the drive channel is greater than a data amount threshold, and outputs a second detection signal when the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold; the control circuit outputs a first control signal based on the first detection signal; and outputs a second control signal based on the second detection signal; and the output circuit outputs the drive signal to the display panel at a first slew rate based on the second control signal; and output the drive signal to the display panel at a second slew rate that is a boosted slew rate based on the first control signal.

The present disclosure provides a processor, an instruction fetching method, and a computer system. The processor includes at least one processor core including an instruction fetch unit and a decoding unit; the instruction fetch unit is configured to perform detection of loop body flag instructions on acquired instructions; and send loop body instructions and non-loop body instructions in the acquired instructions to the decoding unit in a time-sharing manner according to a detection result, with the loop body flag instructions carrying a target number of loops of a loop body, and the instruction fetch unit cyclically sending the loop body instructions to the decoding unit according to the target number of loops; and the decoding unit is configured to decode received instructions.

A display driving method includes: receiving a current image frame; generating a vertical porch corresponding to the current image frame according to a current image transmission speed of an application processor (AP); and driving a display screen to display the current image frame according to the vertical porch corresponding to the current image frame.

A method and apparatus for data writing and reading relate to the field of storage. The data writing method includes: during data writing, re-sorting various subdata contained in target data to generate a writing sequence, wherein the writing sequence is different from an original arrangement sequence of the subdata in the target data; executing writing operation on the subdata according to the writing sequence; and locking the writing sequence, or prohibiting execution of an action for generating the writing sequence after determining that the writing operation is executed on all the subdata. By re-sorting the subdata of the target data and writing the data in a manner of disturbing the original arrangement sequence, the difficulty in cracking data stored in a memory can be increased, and the security of data storage can be ensured.

Disclosed is a processing device, a system, a method for board writing display. The processing device comprises: an extraction unit to extract a first board-writing image from a first image frame in a video and a second board-writing image from a second image frame in the video; a supplement unit to determine an occlusion area of the second board-writing image based on a target object segmentation image of the second image frame, and replace the occlusion area of the second board-writing image with a corresponding area of the first board-writing image to obtain a third board-writing image; an output unit to generate an output image frame based on the second image frame and the third board-writing image, the output image frame presents an image with a target object located behind a transparentized board writing content. The present disclosure enables the board-writing data in the video to be presented completely.

The present application provides a smart card interface, a data transmission method and a television chip. A first memory of the smart card interface is used for caching multiple pieces of indicator data corresponding to a video stream for a TV chip, and the multiple pieces of indicator data are used for determining a decryption key for the video stream. The transmitter is used for transmitting the multiple pieces of indicator data to a smart card sequentially; checking the multiple pieces of indicator data transmitted to the smart card to obtain a first check result of each of the multiple pieces of indicator data, where the first check result is used for indicating whether the smart card has successfully received the corresponding indicator data; and for any indicator data, determining whether to retransmit the indicator data to the smart card based on the first check result of the indicator data. The receiver is used for receiving multiple key data packets corresponding to the decryption key transmitted from the smart card, and caching the multiple key data packets in the second memory. By solutions of the present application, the efficiency of data transmission may be improved, and the problem of playback buffering of TV programs due to data transmission errors may be reduced.

The present application provides a delay clock circuit, a signal transmission device and a method for determining delay, and relates to the field of circuit technologies. The delay clock circuit includes: a self-activation module, including a first inverter and a delay circuit, and used for generating a self-activation clock signal, where the first inverter is connected to an input end of the delay circuit and an output end of the delay circuit respectively; a first counter, connected to the self-activation module, and used for starting to work under a drive of the self-activation clock signal and a start counting signal and stopping working under a drive of a stop counting signal to obtain a first counting result within a preset duration; and a count processing module, connected to the first counter, and used for obtaining a delay of the delay circuit based on the preset duration and the first counting result. The present application can perform calculations based on an accumulated delay counted by the first counter to obtain an accurate delay of the delay circuit. Therefore, an application requirement of a controllable and flexible adjustable delay of the delay circuit in different scenarios is satisfied, and stable and reliable data transmission is achieved.

There are provided a channel coding method, a processing device, a communication method and a device. The channel coding method includes: using a generating matrix or a check matrix of QC-LDPC codes to channel-encode or channel-decode a code stream, wherein a code rate of the generating matrix or the check matrix is 1/6, 1/4 or 1/3. The method can be used in a transmission environment with a low signal-noise ratio and a long distance.