Cadence Design Systems, Inc.

The present disclosure relates to a computer-implemented method for automatically partitioning an electronic design. Embodiments may include accessing, using the at least one processor, the electronic design and partitioning the electronic design using a multi-mode partitioning methodology. Embodiments may further include defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies and performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.

Phase interpolation techniques for clock and data recovery in high-speed serial interfaces. A phase interpolator interpolates between four input clock signals phase-offset by 90 degrees to generate eight output clock signals phase-offset by 45 degrees. The phase interpolator includes primary and secondary mixers that adjust phase values using a mixed thermometer-binary encoding scheme. The primary mixers use most-significant-bit (MSB) thermometer bits for coarse steps and least-significant-bit (LSB) thermometer and binary bits for fine half-steps. The secondary mixers additionally employ boundary bits to maintain proper phase relationships across quadrant transitions. The encoding scheme can reduce routing complexity while preserving monotonic phase progression over the full 360-degree range.

Examples relate to a receiver termination detection circuit for wireline datalinks. A transmitter circuit includes positive and negative output nodes coupled through a channel to a receiver. A detection circuit comprises programmable pull-up and pull-down resistors coupled to the output nodes, and voltage comparators with independent reference voltage inputs. A mode selection input selects between single-ended and differential detection modes. Control logic drives the output nodes concurrently in single-ended mode and differentially in differential mode. The comparator outputs are sampled after a programmable time delay to detect receiver termination. The circuit supports both AC-coupled single-ended and DC-coupled differential termination detection while maintaining common-mode voltage during transitions to normal operation.

Various embodiments provide for adjusting routing capacity of a grid cell of one or more layers of a circuit design based on detected regions, such as notch regions (e.g., corners of macros, blockage corners) and input/output (IO) pin regions. More particularly, various embodiments detect one or more notch regions in a circuit design, detect one or more I/O pin regions in the circuit design, and adjust (e.g., reduce) routing capacity of one or more grid cells of one or more detected regions.

A hybrid window scheme for defining timing windows during CTS. CTS is performed to generate an intermediate clock tree including a respective insertion delay for each of the one of more flip-flops. A set of clock timing constraints is generated for the plurality of slack values of each flip-flop such that every positive slack value of the plurality of slack values is prevented from becoming negative, a lowest negative slack value of the one or more negative slack values is prevented from becoming lower, and every negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than its current value. A second iteration of CTS is performed, constrained by the clock timing constraints, resulting in an enhanced clock tree.

Various example embodiments provide for injecting multiple faults in parallel into a circuit design during fault simulation of the circuit design based on functional independence of the faults, where the fault injection and simulation may be performed as part of an electronic design automation (EDA) software system. According to various example embodiments, a structural analysis of a circuit design is performed to determine fault observability per strobe and the results of the analysis are used to determine independent fault groups for parallel injection during fault simulation of the circuit design.

Embodiments included herein are directed towards a sampler circuit. Embodiments may include a first positive-channel metal oxide semiconductor (PMOS) or negative-channel metal oxide semiconductor (NMOS) transistor that may be operatively connected to a voltage source and a first output node. A cross-coupled PMOS/NMOS pair may be operatively connected to the first PMOS/NMOS transistor, respectively, and a pair of first stage output nodes may be operatively connected to the cross-coupled PMOS/NMOS pair, respectively, where the pair of first stage output nodes may include a positive node and a negative node. An input differential pair may be operatively connected to the pair of first stage output nodes, and an offset current digital-to-analog converter (DAC) may be operatively connected to a first side of the input differential pair, while an offset current DAC replica may be operatively connected to a second side of the input differential pair.

Methods and systems are provided for training an equalizer of a receiver. The methods and systems access a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions and instruct an analog-to-digital converter (ADC) to sample the training sequence to generate a first set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions to an equalizer. The methods and systems cause the ADC to periodically slip sampling of the training sequence to generate a second set of digital symbols in which the plurality of unscrambled portions of the training sequence are randomized and train one or more coefficients of the equalizer using the first set of digital symbols and the second set of digital symbols.

Various example embodiments provide for handling phase interpolator (PI) integral non-linearity (INL) errors based on phase error measurements, which can be used in conjunction with clock data recovery (CDR) within a circuit, such as a data serializer/deserializer (SerDes) circuit. In particular, various example embodiments provide a PI system configured to measure and handle (e.g., reduce or correct) PI integral INL errors, where the PI system comprises a PI, a phase detector, a first-order path, a second-order loop, a phase integrator, a measurement component, and a look-up-table (LUT) component. For various example embodiments, the measurement component is configured to receive phase error information for an input data signal from the phase detector, receive frequency offset information from the second-order loop, receive phase position data for the input signal to the PI, and adjust mappings of one or more phase positions to the PI to reduce or correct non-linearity in the PI.

Dynamically updating a delay line code. A circuit for updating a delay line code is provided having a delay line having a first chain of interleaved logic gates and a second chain of interleaved logic gates. The circuit further include a first clock path generated based upon the first chain of interleaved logic gates and a second clock path generated based upon the second chain of interleaved logic gates, wherein an output of at least one logic gate is forced to zero prior to performing a code update.