CHANGXIN MEMORY TECHNOLOGIES, INC.

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.

Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.

Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.

Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.

Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.

Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.

Methods and equipment for applying photoresist uniformly onto wafers, forming patterns through various exposure techniques (e.g., direct imaging, multi-exposure), and integrating patterned layers into semiconductor structures or packaging.

Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.

Integration of dedicated physical structures or built-in circuitry within semiconductor devices to enable characterization of process variations, material properties, electrical leakage, or device performance.

Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.

Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.

Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Innovations in the design, materials, and manufacturing of lithography masks, including reflective masks, programmable masks, and defect mitigation strategies, to enable finer feature patterning and process control.

Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.

Techniques and apparatus for measuring critical dimensions, overlay accuracy, defect detection, and surface topography in lithographic processes, often involving optical, laser, or charged particle beams.

Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.

Techniques and systems for real-time or near-real-time measurement and adjustment of semiconductor manufacturing parameters (e.g., temperature, etch rate, ion beam uniformity) to ensure process quality and consistency.

Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.

Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.

Development of novel chemical compositions for photoresists, including polymers, sensitizers, and crosslinking agents, to achieve improved lithographic performance such as resolution, sensitivity, line edge roughness, and etch resistance.

Methods for depositing thin films with controlled conformality, thickness, and material properties, including selective deposition on specific areas, often using atomic layer deposition (ALD), chemical vapor deposition (CVD), or epitaxial growth.

Devices and methods for accurately measuring or monitoring electrical current draw and power usage in various systems, often for control, optimization, or safety purposes.

Utilizing optical systems, cameras, and image processing algorithms for precise measurement of physical dimensions, alignment, defects, and features on semiconductor wafers or packages.

Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Components, processes, and methods specifically designed for Extreme Ultraviolet (EUV) lithography, including light sources, reflective optics, masks, pellicles, and contamination control mechanisms.

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Methods and systems for identifying anomalies, failures, or impending issues within electric motors or their associated drive and power management circuits, often by monitoring electrical or operational parameters.

Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.

Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.

Physical layout and material composition of individual pixels within a display panel, including active layers, electrodes, light-emitting elements (LEDs, OLEDs), and associated thin-film transistors (TFTs).

Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.