CHIPBOND TECHNOLOGY CORPORATION

Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.

Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.