CROSSBAR, INC.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

A secure peer-to-peer network is implemented with computing devices over unsecure network connections. Each computing device can include or be coupled to a proof of origin hardware. The proof of origin hardware can be validated by publicly available data, such as a trusted server or by secure storage of valid proof of origin data, or other modality. Once validated on the peer-to-peer network, peer nodes can provide or can receive network services, such as blockchain services, off-chain data oracle services, smart contract-enabled services, distributed data oracle services, distributed network gateway services, among others.

A secure peer-to-peer network is implemented with computing devices over unsecure network connections. Each computing device can include or be coupled to a proof of origin hardware. The proof of origin hardware can be validated by publicly available data, such as a trusted server or by secure storage of valid proof of origin data, or other modality. Once validated on the peer-to-peer network, peer nodes can provide or can receive network services, such as blockchain services, cryptocurrency transaction services, smart contract-enabled services, token exchange, survey services leveraging proof of origin data, distributed data backup services, distributed computing services, among others.

A secure peer-to-peer network is implemented with computing devices over unsecure network connections. Each computing device can include or be coupled to a proof of origin hardware. The proof of origin hardware can be validated by publicly available data, such as a trusted server. In addition, the proof of origin hardware can facilitate cryptographic key generation to facilitate encryption of communications at the computing devices, to secure such communications over the unsecure network connections. The proof of origin hardware can include hardware acceleration circuitry to provide network services, such as cryptocurrency transactions, blockchain validation computations, and even blockchain services integrating smart contracts, token exchange, survey services leveraging proof of origin data, distributed data backup, distributed computing, among others.

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

Backup and recovery of multi-party computation (MPC) security data utilized to secure digital assets and transactions thereof can enhance user confidence and user experience in digital asset transactions. Example MPC security data can include cryptographic keys and key shares utilized with a N×M MPC signature and validation framework. A computing device participating in generation of MPC secure data can retain a segment of the MPC secure data and can encrypt and store an encrypted segment at a second device. A recovery service or recovery application at the second device can facilitate recovery of the MPC secure data segment at the computing device, or at an additional device not involved in generation of the MPC secure data. The recovery service or application can facilitate recovery of the MPC secure data segment even in the event the computing device is lost.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

A secure microcontroller for a secure data storage device can utilize two-terminal non-volatile memory for enhanced security and component density. The secure microcontroller can operate portions of the two-terminal memory in different modes, such as OTP, rewritable or MTP, physical unclonable function PUF and so forth, and discriminate among data access requests according to data characterizations defined for data parameters stored at the secure storage device. A link table maintained by the secure microcontroller can correlate these characterizations with distinct data parameters. In some embodiments of the present disclosure, the secure microcontroller can also maintain predefined characterizations that are common to many data sets. In these embodiments, the link table can simply correlate many of the data sets to one of the predefined characterizations and significantly reduce the overhead involved in characterizing many distinct data parameters.

A secure microcontroller for a secure data storage device can utilize two-terminal non-volatile memory for enhanced security and component density. The secure microcontroller can operate portions of the two-terminal memory in different modes, such as OTP, rewritable or MTP, physical unclonable function PUF and so forth, and discriminate among data access requests according to data characterizations defined for data parameters stored at the secure storage device. A link table maintained by the secure microcontroller can correlate these characterizations with distinct data parameters. In some embodiments of the present disclosure, the secure microcontroller can also maintain predefined characterizations that are common to many data sets. In these embodiments, the link table can simply correlate many of the data sets to one of the predefined characterizations and significantly reduce the overhead involved in characterizing many distinct data parameters.

Improved erase techniques enhance longevity of two-terminal non-volatile memory and can mitigate or avoid erase state memory failures. An erase process can include performing an erase operation(s) on a two-terminal memory cell, followed by a weak program operation. An erase-verify process can determine whether the memory cell has a read current within a target range. In one or more embodiments, additional erase and weak program cycles can be implemented to initiate a weakly programmed state that can be defined as an erase state. The weakly programmed state can be configured so that drift or diffusion over time results in higher resistance not reversion to a low resistance state, to mitigate or avoid erase failure of the two-terminal memory cell.