CSMC TECHNOLOGIES FAB2 CO., LTD.

A manufacturing method for a super-β bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.

The present disclosure relates to a single-photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof. The method includes: obtaining a wafer; patterning and etching a front surface of the base to form a quenching resistor trench and an isolation trench, wherein a width of the isolation trench is greater than a width of the quenching resistor trench; forming an insulation layer on an inner surface of the quenching resistor trench; depositing polycrystalline silicon on the front surface of the base, where the polycrystalline silicon is filled into the quenching resistor trench and seals the quenching resistor trench while the polycrystalline silicon is filled into the isolation trench and does not seal the isolation trench; performing oxidation treatment on the polycrystalline silicon in the isolation trench; filling a light-shielding conductive material into the isolation trench.

The present disclosure relates to a trench-type DMOS device and manufacturing method therefor. The trench-type DMOS device includes an expansion gate layer disposed on an inner surface of a gate insulation layer, and the expansion gate layer includes a first expansion gate region with a second conduction type, a second expansion gate region with a first conduction type, and a third expansion gate region, which improves a contradiction relationship between voltage resistance and specific on-resistance of the trench-type DMOS device. Therefore, the trench-type DMOS device has both high voltage resistance and low specific on-resistance. The trench-type DMOS device has a longitudinal voltage resistance structure, which reduces device area and further decreases device on-resistance. At the same time, a source region and a drain region in the trench-type DMOS device may be led out on its front surface, which is compatible with CMOS.

The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

In one aspect, a laterally diffused metal oxide semiconductor (LDMOS) device includes at least one cell structure. The cell structure includes: a substrate; a N-type first well region disposed in the substrate; the first well region being provided with a first region, an isolation region, and a second region that are sequentially arranged in a first direction; a P-type first doped region and a P-type second doped region, the first doped region being located in the first region, and the second doped region being located in the second region; and a P-type source region and a P-type drain region disposed in the substrate and located on two sides of the first doped region in a second direction. The first direction is a width direction of a conductive channel. The second direction is a length direction of the conductive channel.

A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

An IGZO thin-film transistor and a method for manufacturing same. The method includes: acquiring a substrate; forming an IGZO layer on the substrate by a solution process; doping V impurities on a surface of the IGZO layer by a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

In one aspect, a silicon-on-insulator semiconductor device includes: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; and a drift region disposed on the buried dielectric layer. An upper surface of the drift region forms a drop structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side. An upper surface of the second side is higher than a bottom surface of the first side, such that a thickness of the drift region at the second side is greater than that at the first side. The first electrode and the second electrode are configured such that a voltage applied to the second electrode is greater than a voltage applied to the first electrode when a reverse bias voltage is applied to the device.

The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device includes a semiconductor substrate, an insulating buried layer, a drift region, and a plurality of dielectric isolation structures. The insulating buried layer is located on the semiconductor substrate. The drift region is located on the insulating buried layer. A drain region is provided on part of the upper surface of the drift region. The plurality of dielectric isolation structures are located in the drift region and on the insulating buried layer, and are spaced apart from each other in a direction towards the drain region. At least one dielectric isolation structure protrudes from the insulating buried layer and is bent towards the drain region.

In one aspect, a semiconductor device includes: a first metal layer disposed on a substrate; a dielectric layer disposed on a side of the first metal layer distant from the substrate; a second metal layer disposed on a side of the dielectric layer distant from the first metal layer, the potential of the second metal layer being higher than the potential of the first metal layer; and a metal ring disposed on a side of the dielectric layer distant from the first metal layer, the metal ring being arranged around an outer side of the second metal layer. A portion of the metal ring is located in the dielectric layer.