D-WAVE SYSTEMS INC.

The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples may be used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.

A qubit within an analog computing system with two or more body loops is discussed, along with inductors disposed along at least one of the body loops to provide tunable inductance and increase or decrease the qubit capacitance. Near and far inductors can be tuned to homogenize the inductance and capacitance of the qubit across a range of programmable states based on predicted and target inductance and capacitance for the qubit.

A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4 -qubit even-parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing super-conducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb 2 O 5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.

Cable assemblies and, systems using the assemblies can include thermal breaks between assembly sections, and methods for fabricating the assemblies can include creating thermal breaks. A cable assembly includes a first shielding cable having a first solderable material interleaved with a section of a second shielding cable having an exterior material that is a second solderable material and an inner material that is superconductive at and below a critical temperature. The cable assembly may be fabricated during the assembly of an apparatus, and, following assembly of the apparatus, a segment of the second shielding cable is etched to expose a portion of the inner material. Following fabrication of the cable assemblies, the apparatus may be installed in a cryogenic environment in which the exposed portion of superconductive inner material thermally isolates the cabling assembly proximate to a superconducting circuit from the remaining cabling assembly.

An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.

There is provided a system and methods to determine an improved solution to a Mixed Integer Problem (MIP) using a quantum-assisted MIP solver. The methods are performed by a digital processor in communication with a quantum processor. Methods include: selecting at least one feasible solution determined by an MIP solver, determining a first sub-problem of the MIP based on the at least one feasible solution; casting the first sub-problem as Binary Quadratic Models (BQMs); solving the BQMs using the quantum processor to generate sample solutions; determining a second sub-problem based on at least the sample solutions, and obtaining a current solution to the MIP by evaluating the second sub-problem; and updating an incumbent solution if the current solution improves over the current incumbent solution. The quantum-assisted MIP solver uses hybrid crossover and mutation heuristics to improve the convergence time and accuracy of solutions obtained using Branch-and-Cut solvers.

A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.

A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.