D2S, INC.

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

A system may include a device configured to receive a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges; a device configured to determine a neighborhood open area density for the plurality of patterns; and a device configured to determine a geometric loading effect correction (gLEC). The gLEC comprises a calculated offset from an edge in the plurality of edges, where the calculated offset is determined using the neighborhood open area density, and the determining the gLEC is performed offline. A system may also include a device configured to adjust the plurality of edges using the gLEC to counteract a loading effect, where the loading effect is a difference in an amount of etching that occurs based on the neighborhood open area density, forming an adjusted plurality of edges.

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing components of the first layer, including a first component that overlaps with a second component on a second layer. The method identifies a more critical first region and a less critical second region of a first shape of the first component that both overlap with a second shape of the second component. The more critical first region is more important to ensuring overlap of the first shape with the second shape. To improve overlap between the first and second shapes, the method uses different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout.

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Some embodiments provide a method for decomposing a layout into two or more pattern layouts. The method receives, for an IC layer, a first decomposition of a layout. The layout includes shapes that in the first decomposition are individually assigned to at least one pattern layout of the first decomposition. The method identifies violations resulting from the first decomposition. A first set of shapes assigned to a first pattern layout is identified as resulting in a violation while a second set of shapes, assigned to a second pattern layout and having a same set of shapes in a same relative arrangement as the first set of shapes, is not identified as resulting in a violation. Based on the identified violations, the method defines a second decomposition of the layout in which at least two different shapes of the first set of shapes are assigned to different pattern layouts.

Some embodiments provide a method for decomposing a layout for a layer of an integrated circuit (IC) into two or more pattern layouts. The method receives, for the IC layer, a layout having multiple shapes representing a set of components that are to be manufactured on the IC layer. The method decomposes the layout into a first decomposition having a first set of two or more pattern layouts. The method identifies a set of violations in the layout when the first set of pattern layouts are used to manufacture the IC layer. The method computes a decomposition score for the first decomposition based on a size of an area of each identified violation. The method uses the computed score to decompose the layout into a second decomposition that has a second set of pattern layouts to use to manufacture the IC.

Some embodiments provide a method for performing coloring for a design layout for an integrated circuit (IC) layer. The method receives a layout for the IC layer. The layout includes multiple features that represent IC components to be manufactured for the particular layer. The method generates a decomposition of the IC into multiple pattern layouts by using a machine-trained network (MTN) that outputs assignment of each layout feature to one of the pattern layouts. The method uses the pattern layouts for manufacturing the IC layer.

Some embodiments provide a method for decomposing a layout for a first layer of an integrated circuit (IC) into pattern layouts. The method receives a first decomposition of the first IC layer design layout into a first set of two or more pattern layouts. The method generates predicted manufactured shapes for the first IC layer based on the received first decomposition. the method measures manufacturability of the first IC layer when the first IC layer uses the first decomposition based on alignment of the predicted manufactured shapes of the first IC layer with predicted manufactured shapes of at least a second IC layer. The method uses the measure of manufacturability to decompose the layout into a second decomposition that has a second set of pattern layouts to use to manufacture the IC.