Deca Technologies USA, Inc.

An electronic assembly with a molded bridge, vertical interconnects and encapsulant disposed around vertical interconnects. A first build-up interconnect structure disposed over the encapsulant and the vertical interconnects, through conductive interconnects disposed in a periphery of the molded bridge, a second encapsulant disposed over the molded bridge and around the through conductive interconnects. A second build-up interconnect structure disposed over the molded bridge, the second encapsulant, and the through conductive interconnects. To make the assembly, a first encapsulant is disposed around and over vertical interconnects disposed over a carrier, a first build-up interconnect structure is formed over the first encapsulant and the vertical interconnects, and through conductive interconnects are disposed in a periphery of the vertical interconnects. A second encapsulant is disposed over the first encapsulant, the vertical interconnects and through conductive interconnects to form a molded base, and a second build-up interconnect structure is formed over the molded base.

A method of making a semiconductor assembly may include providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and contacting at least four side surfaces of the semiconductor component and disposed over frontside of the semiconductor component. A first layered structure may be formed as a build-up interconnect structure over the encapsulant and over the semiconductor component. The first layered structure may comprise a first conductive layer formed over the first encapsulant, a first dielectric formed over the first conductive layer, and a second encapsulant disposed over first conductive layer and over first dielectric. An upper surface of the second encapsulant may be planarized to create a flat surface on which to form additional structures, such as a second layered structure or a package interconnect.

A semiconductor assembly includes a bridge component without vias extending through the bridge component. The bridge component includes one or more interconnect layers over a frontside of the bridge and an outermost interconnect layer coupled to conductive studs. Conductive vertical interconnects are in a periphery of the assembly with an encapsulant on five sides of the bridge component, on sides of the conductive studs, and on sides of the conductive vertical interconnects that leave ends of the conductive studs and ends of the conductive vertical interconnects coplanar with top and bottom surfaces of the encapsulant. A frontside build-up interconnect structure is over the conductive studs and couple to first ends of the conductive vertical interconnects. The frontside build-up interconnect includes first pads at a first pitch within a footprint of the bridge component and second pads at a second pitch outside a footprint of the bridge component.

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

A method of making a semiconductor assembly may include mounting a plurality of components to a patterned element on an intermediate carrier, and disposing an encapsulant over the intermediate carrier, where the encapsulant may be disposed around four side surfaces of each of the plurality of components and one or more of the plurality of components may comprise conductive studs disposed over a front surface of the components. The method may further include removing a portion of the encapsulant to form a planar surface above the front surface, wherein the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant. The method may further comprise removing the intermediate carrier through a grinding process, and terminating the grinding process when at least a portion of the patterned element is exposed.

An electronic assembly with a molded bridge, vertical interconnects and encapsulant disposed around vertical interconnects. A first build-up interconnect structure disposed over the encapsulant and the vertical interconnects, through conductive interconnects disposed in a periphery of the molded bridge, a second encapsulant disposed over the molded bridge and around the through conductive interconnects. A second build-up interconnect structure disposed over the molded bridge, the second encapsulant, and the through conductive interconnects. To make the assembly, a first encapsulant is disposed around and over vertical interconnects disposed over a carrier, a first build-up interconnect structure is formed over the first encapsulant and the vertical interconnects, and through conductive interconnects are disposed in a periphery of the vertical interconnects. A second encapsulant is disposed over the first encapsulant, the vertical interconnects and through conductive interconnects to form a molded base, and a second build-up interconnect structure is formed over the molded base.

Disclosed is an assembly comprising a 3D block comprising a support material disposed around a conductive element, where the support material comprises a cut or ground edge and a portion of a wafer, the assembly further comprising at least one component disposed adjacent the 3D block, and an encapsulant disposed around the 3D block and around the at least one component, and a first interconnect structure formed over, and coupled with, first ends of the conductive elements, where the first ends are exposed with respect to the support material.

A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

The disclosure concerns methods of forming a semiconductor device with a repairable redistribution layer (RDL) design, comprising: preparing an original repairable RDL design; forming first conductive segments of the repairable RDL design; inspecting the first conductive segments of the repairable RDL design to detect manufacturing defects; detecting at least one defect in the first conductive segments; and forming second conductive segments of the repairable RDL design according to a new custom RDL design to mitigate the negative effects of the at least one defect among the first conductive segments. The disclosure also concerns semiconductor devices with a repairable RDL design.

A method of making a semiconductor assembly may include mounting a plurality of components to one or more intermediate carriers and disposing the one or more intermediate carriers over a temporary carrier. The intermediate carriers may comprise one or more conductive features and coupling the components to the conductive features. The method may further include disposing an encapsulant over the one or more intermediate carriers and over the plurality of components mounted to the temporary carrier to form a reconstituted panel. The encapsulant may be disposed around four side surfaces and over a front surface of each of the plurality of components and removing a portion of the encapsulant to form a planar surface above the front surface of the plurality of components and removing the temporary carrier.