Elite Semiconductor Microelectronics Technology Inc.

A signal recovery system includes multiple frequency dividers, multiple signal recovery circuits, and a data signal generating circuit. The multiple frequency dividers perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit generates a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

A write leveling system includes a frequency divider, a signal processing circuit, and a data control circuit. The frequency divider is arranged to perform a frequency dividing operation upon a clock signal to generate multiple frequency-divided clock signals. The signal processing circuit is arranged to perform signal processing upon a data strobe signal to generate multiple processed data strobe signals. The data control circuit is arranged to generate a data signal according to the multiple frequency-divided clock signals and the multiple processed data strobe signals, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

A signal recovery system includes multiple frequency dividers, multiple signal recovery circuits, and a data signal generating circuit. The multiple frequency dividers perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit generates a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

A write leveling system includes a frequency divider, a signal processing circuit, and a data control circuit. The frequency divider is arranged to perform a frequency dividing operation upon a clock signal to generate multiple frequency-divided clock signals. The signal processing circuit is arranged to perform signal processing upon a data strobe signal to generate multiple processed data strobe signals. The data control circuit is arranged to generate a data signal according to the multiple frequency-divided clock signals and the multiple processed data strobe signals, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

A repairable semiconductor memory device includes an input/output bus, a plurality of stacked memory chips, and a redundant repair unit. Each of the memory chips compares a memory address information with an address information to be repaired to generate a first comparison result for determining whether to allow the input/output bus to access the data corresponding to the memory address information in the memory chips. The redundancy repair unit compares the memory address information with the address information to be repaired to generate a second comparison result for determining whether to allow a redundant memory cell corresponding to the memory address information to be coupled to the input/output bus. In this way, the semiconductor memory device can repair any layer of the memory chips to improve the yield to solve the problem of previously having a lower yield.

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.

A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects g m degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.