EM Microelectronic-Marin SA

A data reading system including two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.

An electronic circuit and method of sorting data elements provided in a memory array. The method includes: assigning a comparison counter to each data element; comparing a first data element stored in a first memory area with all further data elements stored in the number of memory areas; incrementing a counter value of the comparison counter of the first data element if the comparison of the first data element with any one of the further data elements matches a predefined comparison condition, else incrementing the comparison counter of the other data element; comparing further data elements with all subsequent data elements, and incrementing each associated counter value upon the success of the comparisons; and sorting the data elements on the basis of the comparison counters.

A method for managing data stored in a page (P) within a memory element of a memory system including a controller, the page (P) including at least one encoded data (E) consisting in a binary code being formed by a word (W 0 -N) and its associated redundancy code (RC 0 -N), the method including a step of storing a user data in this page (P) implemented by the controller, this step including a sub-step of performing error correction code (ECC) calculations on the user data providing an associated redundancy code (RC 0 -N) corresponding to an erased redundancy code (RC E) for this user data if it has a reference binary code (br) of an erased word (W E) the erased redundancy code (RC E) having a binary value similar to that of the reference binary code (br).

A method for reading data from a non-volatile memory array having memory cells configured to store one bit information, including powering on the array, where information from at least first and second memory cells is collectively associated with one bit of sensible data; reading first and second memory cell values by comparing a reference value to an electrical property value of the respective memory cell; adjusting the reference value when at least the first and second memory cell values have a first combination of logic state values; reading the first and second memory cell values using the adjusted reference value to obtain a second combination of logic state values; and determining a sensible data bit value based on the second combination. The adjusted reference value lies in the space between first and second distributions of possible electrical property values respectively for the first and second memory cell values.

A method for managing data stored in a page (P) within a memory element of a memory system including a controller, the page (P) including at least one encoded data (E) consisting in a binary code being formed by a word (W 0 -N) and its associated redundancy code (RC 0 -N), the method including a step of storing a user data in this page (P) implemented by the controller, this step including a sub-step of performing error correction code (ECC) calculations on the user data providing an associated redundancy code (RC 0 -N) corresponding to an erased redundancy code (RC E) for this user data if it has a reference binary code (br) of an erased word (W E) the erased redundancy code (RC E) having a binary value similar to that of the reference binary code (br).

A method for reading data from a non-volatile memory array including a plurality of memory cells, each configured to store one bit of information. The method includes the steps of: powering on the memory array, where information from at least a first memory cell and a second memory cell is collectively associated with one bit of sensible data; b) reading a first memory cell value and a second memory cell value by comparing a reference value to a respective electrical property value of the respective memory cell to determine the respective memory cell value; c) adjusting the reference value in the event at least the first and second memory cell values have a first combination of logic state values to obtain an adjusted reference value; d) reading the first and second memory cell values by using the adjusted reference value to obtain a second combination of logic state values; and e) determining a sensible data bit value based on the obtained second combination of logic state values.

An address decoder unit ( 30 ) for a memory cell array ( 10 ), the address decoder unit ( 30 ) including an address decoder ( 31 ) including an address input ( 33 ) and a number of address outputs ( 34, 35, 36 ), the address decoder ( 31 ) being operable to select one of the address outputs ( 34, 35, 36 ) in response to receive a memory address at the address input ( 33 ); and an address selection circuitry ( 32 ) connected to the address decoder ( 31 ) and including a number of address selection outputs ( 44, 45, 46 ) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit ( 30 ) is switchable into a memory erase mode, in which the address selection circuitry ( 32 ) is operable to select all address selection outputs ( 44, 45, 46 ) of an address space above or beyond a memory address provided at the address input ( 33 ).

The present invention concerns an anti-tearing protection system ( 1 ) for a non-volatile memory ( 3 ) comprising a first memory block ( 5 ) and a second memory block ( 7 ), the first and second memory blocks ( 5, 7 ) being arranged to store a data set comprising user data and an error detection code obtained based on the user data. The first and second memory blocks ( 5, 7 ) can be read in a first read mode for determining logic states of data elements comprised in the data set according to the first read mode. The user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value. The first and second memory blocks ( 5, 7 ) can further be read in a second read mode for determining the logic states of the data elements comprised in data set according to the second read mode. The user data in a respective memory block are considered to be correct according to the second read mode if its error detection code equals the first given value and if the user data as read in the second read mode are determined to be identical to the user data as read in the first read mode. A third read mode may also be defined. The first read mode may be considered to be a normal read mode, while the second and third read modes may be used to determine if data were strongly written and erased, respectively.