UnfoldIPThemes

Company patents

ETRON TECHNOLOGY, INC.

Etron Technology, Inc.'s patent strategy reveals a strong, recent surge in core semiconductor areas, with "Memory Devices (Structural)" (36.0% of portfolio) and "Multi-Chip & 3D Assemblies" (30.0% of portfolio) showing significant growth of +70.0% and +55.6% respectively in 2025, following even higher growth in 2024. However, the sharp decline in patenting activity across nearly all categories so far in 2026, including a 100.0% drop in "Transistor & Device Structure" and "Integrated Circuit Layout & Arrangement," suggests a potential shift or slowdown in their innovation output compared to the preceding years.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

100 US filings (since 2023) · 12 categories · 23 themes

Novel Memory Transistor Architectures

Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.

Transistor & Device Structure
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40since 2023
+25.0%YoY
Advanced Memory Cell Structures

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Memory Devices (Structural)Memory & Storage (Static)
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37since 2023
+112.5%YoY
3D Die Stacking & Vertical Interconnects

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Multi-Chip & 3D AssembliesSemiconductor Packaging & EncapsulationMemory Devices (Structural)Chip-to-Chip Interconnect (Bonding, Bumps)Semiconductor Diodes & Transistors
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32since 2023
+40.0%YoY
Gate-All-Around Transistors

Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.

Semiconductor Diodes & Transistors
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21since 2023
-54.5%YoY
Heterogeneous Chiplet Integration

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Multi-Chip & 3D AssembliesMemory Devices (Structural)
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20since 2023
-33.3%YoY
Advanced Transistor Device Architectures

Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.

Integrated Circuit Layout & Arrangement
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17since 2023
-81.8%YoY
Semiconductor Device Manufacturing Processes

Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.

Transistor & Device Structure
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14since 2023
-70.0%YoY
Resistive & Phase Change Memoryfiltered

Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.

Memory Devices (Structural)
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13since 2023
-20.0%YoY
FinFET & Multigate Device Fabrication

Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.

Transistor & Device Structure
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10since 2023
-85.7%YoY
Integrated Circuit Interconnect & Layout Optimization

Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.

Integrated Circuit Layout & Arrangement
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9since 2023
-20.0%YoY
Backside Contact & Interconnects

Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.

Transistor & Device Structure
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8since 2023
-40.0%YoY
Memory System Performance & Reliability

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Memory & Storage (Static)Computer Hardware Architecture
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8since 2023
0.0%YoY
Gate Stack & Dielectric Engineering

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Semiconductor Diodes & TransistorsTransistor & Device Structure
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6since 2023
+300.0%YoY
Novel Logic & Memory Circuit Elements

Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.

Integrated Circuit Layout & Arrangement
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6since 2023
-33.3%YoY
Advanced Metallization & Contacts

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Semiconductor Diodes & TransistorsChip-to-Chip Interconnect (Bonding, Bumps)
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5since 2023
+100.0%YoY
Memory Reliability, Testing & Repair

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.

Memory & Storage (Static)
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4since 2023
+100.0%YoY
Package Thermal Management

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Multi-Chip & 3D AssembliesSemiconductor Packaging & EncapsulationChip-to-Chip Interconnect (Bonding, Bumps)Semiconductor Manufacturing Process
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4since 2023
-50.0%YoY
Fan-Out & Embedded Die Packaging

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Semiconductor Packaging & EncapsulationMulti-Chip & 3D AssembliesChip-to-Chip Interconnect (Bonding, Bumps)
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2since 2023
new
In-Memory Sensing & Data Path

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Memory & Storage (Static)
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2since 2023
n/a
High-Speed Data Interconnects

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Computer Hardware Architecture
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2since 2023
n/a
On-Chip Sensing & Display Integration

Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.

Semiconductor Diodes & Transistors
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1since 2023
new
Wide Bandgap Power Devices

Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.

Semiconductor Diodes & Transistors
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1since 2023
new
Advanced Package Interconnects

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Semiconductor Packaging & Encapsulation
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1since 2023
n/a

Patents

Showing 1-10 of 22

Resistive & Phase Change Memory
Page 1 of 3
US 12597465 B2GRANTED
G11C11/419

Memory device

Filed:2024-02-23Pub:2026-04-07
Applicant:Etron Technology, Inc.

A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.

US 12439588 B2GRANTED
H10B12/00

Method of forming a memory cell with a transistor and a capacitor

Filed:2023-09-18Pub:2025-10-07
Applicant:Etron Technology, Inc.

The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

US 12417798 B2GRANTED
G11C11/4091

Semiconductor memory structure

Filed:2023-04-26Pub:2025-09-16
Applicant:Invention And Collaboration Laboratory Pte. Ltd.

A semiconductor memory structure includes a plurality of DRAM cells, a bit line, and a sense amplifier. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. A capacitance of the bit line per DRAM cell is lower than 20×10 −3 fF.

US 12361998 B2GRANTED
G11C11/4074

Sustainable DRAM having principle power supply voltage unified with logic circuit

Filed:2021-05-28Pub:2025-07-15
Applicant:ETRON TECHNOLOGY, INC.

This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

US 12354646 B2GRANTED
G11C11/4091

Dynamic memory with sustainable storage architecture

Filed:2022-04-10Pub:2025-07-08
Applicant:Etron Technology, Inc.

The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

US 20240363156 A1APPLICATION
G11C11/4074

DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT

Filed:2024-07-12Pub:2024-10-31
Applicant:Etron Technology, Inc.

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

US 12082400 B2GRANTED
H10B12/00

Memory cell structure with capacitor over transistor

Filed:2021-05-05Pub:2024-09-03
Applicant:Etron Technology, Inc.

A memory cell structure includes a silicon substrate, a transistor, a bit line, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The bit line is electrically coupled to the first conductive region of the transistor and positioned under the silicon surface. The capacitor is over the transistor and electrically coupled to the second conductive region of the transistor.

US 20240290380 A1APPLICATION
G11C11/419

MEMORY DEVICE

Filed:2024-02-23Pub:2024-08-29
Applicant:Etron Technology, Inc.

A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.

US 12068020 B2GRANTED
G11C11/4074

Dynamic memory with sustainable storage architecture and clean up circuit

Filed:2022-01-12Pub:2024-08-20
Applicant:Etron Technology, Inc.

The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

US 20240008256 A1APPLICATION
H10B12/00

MEMORY CELL STRUCTURE

Filed:2023-09-18Pub:2024-01-04
Applicant:Etron Technology, Inc.

The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

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