Ferroelectric Memory GmbH

Various aspects relate to a method including: forming a plurality of memory cells, wherein each of the plurality of memory cells includes a respective spontaneously-polarizable memory element in an as-formed condition; carrying out a preconditioning operation to concurrently bring the respective spontaneously-polarizable memory element of each of the plurality of memory cells from the as-formed condition into an operable condition to allow for a writing of each of the plurality of memory cells after the preconditioning operation is carried out; wherein the preconditioning operation includes providing a periodic precondition signal at each memory cell of the plurality of memory cells, wherein each cycle of the periodic precondition signal includes a first precondition voltage pulse having a first polarity and a second precondition voltage pulse having a second polarity opposite to the first polarity, and wherein the periodic precondition signal has a frequency equal to or less than 150 Hz.

A cell operation circuit for operating a set of memory elements comprises: an access circuitry comprising a first input terminal and a second input terminal and being configured to receive a first operation voltage at the first input terminal and to receive a second operation voltage at second input terminal to access a first memory element of the set; a control circuitry configured to provide a protection voltage, to which a second memory element of the set is exposed, when the first memory element is accessed by the access circuitry, wherein the protection voltage is between the first operation voltage and the second operation voltage.

Disclosed herein are devices, methods, and systems for reading a programmed state of a memory element. The method includes setting a bit line to which the memory element is connected to a first voltage and developing to the bit line a compensation voltage different from the first voltage. The method also includes developing a modified sensing voltage to the bit line defined by the compensation voltage and a sensing voltage developed from the memory element and determining the programmed state based on the modified sensing voltage. A complementary memory element may be used to develop the compensation voltage by discharging a complementary plate line, to which the second memory element is connected, to charge a complementary bit line to which the second memory element is connected and by connecting the bit line to the complementary bit line to develop the compensation voltage to the bit line.

Various aspects relate to a memory cell arrangement including: a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes a respective remanent-polarizable memory layer; and a controller configured to cause a conditioning operation for each memory cell of a first subset of memory cells of the plurality of memory cells, the conditioning operation including for a respective memory cell of the first subset of memory cells: reading a memory state of the respective memory cell and writing an assigned memory cell of a second subset of memory cells of the plurality of memory cells into the memory state, the second subset of memory cells being different from the first subset of memory cells; and, subsequently, causing an alternating sequence of voltage drops of opposite polarities over the respective remanent-polarizable memory layer of the respective memory cell.

Disclosed herein is a cell operation circuit for sensing a programmed state of a memory element comprising: a sensing circuitry comprising a sensing node, a first input terminal to receive a first operation voltage and a second input terminal to receive a second operation voltage less than the first operation voltage; a first switch configured to apply a pre-charge voltage less than the second operation voltage to the sensing node; wherein the sensing circuitry is configured to read from the memory element based on a sensing voltage, which is developed at the sensing node.

A memory cell may comprise a field-effect transistor structure comprising a gate structure, the gate structure comprising a floating gate electrode separated from a channel of field-effect transistor structure by a gate isolation; a spontaneously polarizable memory layer, wherein the spontaneously polarizable memory layer covers completely an upper surface of the floating gate electrode and wherein the spontaneously polarizable memory layer covers one or more lateral surfaces of the floating gate electrode; a gate electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the gate electrode to form a capacitive memory structure; and a lever electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the lever electrode to form a lever structure.

Disclosed herein are devices, methods, and systems for calibrating a read voltage level for reading memory cells of a memory. The calibration circuit includes a reference cell associated with a predefined programming state of the reference cell. The calibration circuit also includes a read circuit configured to (e.g., until a read state of the reference cell matches the predefined programming state), perform a read operation on the reference cell at a reference read voltage level to obtain a read state of the reference cell and adjust the reference read voltage level to an adjusted reference read voltage level based on a comparison between the read state and the predefined programming state. The read circuit is configured to provide the adjusted reference read voltage level to the memory as the read voltage level for reading the memory cells of the memory.

Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure comprises a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

Memory cell arrangements and methods of operating a memory cell are disclosed, wherein a memory cell arrangement includes a memory cell including: a field-effect transistor including a gate terminal, a first source/drain terminal, and a second source/drain terminal; and a spontaneously-polarizable capacitor connected to the first source/drain terminal of the field-effect transistor, the spontaneously-polarizable capacitor having a first capacitance; and a write modification circuit electrically conductively connected to the second source/drain terminal or to the spontaneously-polarizable capacitor, wherein the write modification circuit includes a write capacitor having a second capacitance and wherein the write modification circuit is configured to selectively provide the second capacitance when the memory cell is written.

Disclosed herein are devices, methods, and systems for calibrating a read voltage level for reading memory cells of a memory. The calibration circuit includes a reference cell associated with a predefined programming state of the reference cell. The calibration circuit also includes a read circuit configured to (e.g., until a read state of the reference cell matches the predefined programming state), perform a read operation on the reference cell at a reference read voltage level to obtain a read state of the reference cell and adjust the reference read voltage level to an adjusted reference read voltage level based on a comparison between the read state and the predefined programming state. The read circuit is configured to provide the adjusted reference read voltage level to the memory as the read voltage level for reading the memory cells of the memory.