FLOSFIA INC.

Provided a semiconductor device having a structure to suppress hole injections into the gate insulator. A semiconductor device including a gate insulating film, a hole blocking layer placed in contact with the gate insulating film, and an oxide semiconductor layer placed in contact with the hole blocking layer, wherein the hole blocking layer is located between the gate insulating film and the oxide semiconductor layer.

Provided is a semiconductor device, including: a gate electrode having at least a part buried in a semiconductor layer; a deep p layer having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and a channel layer, wherein: the deep p layer is formed by a crystalline oxide semiconductor; and a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer.

The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).

A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.

Provided is a semiconductor device including; at least a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of a c-axis in the semiconductor layer being the first direction.

A semiconductor device with an enhanced semiconductor characteristics that is useful for power devices. A semiconductor device including: a semiconductor region; a barrier electrode arranged on the semiconductor region; and two or more adjustment regions of barrier height that are on a surface of the semiconductor region and arranged between the semiconductor region and the barrier electrode, the adjustment regions are configured such that barrier height at an interface between the adjustment regions and the barrier electrode is higher than barrier height at an interface between the semiconductor region and the barrier electrode.

Provided is a semiconductor device comprising at least, a high-resistance oxide film, which is placed in a direction in which a current flows, the high-resistance oxide film having a resistance of 1.0×10 6 Ω·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; and a high-resistance oxide film, which is placed between the source electrode and the drain electrode and has a resistance of 1.0×10 6 Ω·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; a high-resistance oxide film; and a substrate with the high-resistance oxide film being placed between the source electrode or/and the drain electrode and the substrate and having a resistance of 1.0×10 6 Ω·cm or higher.

An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer, a dielectric film provided on the semiconductor layer and having an opening and provided over a distance of at least 0.25 μm from the opening, and an electrode layer provided over a part or all of the dielectric film from the inside of the opening, wherein the dielectric film has a thickness of less than 50 nm from the opening to a distance of 0.25 μm, and has relative permittivity of 5 or less.

An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer including an oxide semiconductor having a corundum structure as a main component, and a Schottky electrode including a first electrode layer and a second electrode layer having a higher conductivity than the first electrode layer, wherein an outer edge portion of the second electrode layer is electrically connected to the semiconductor layer at an electrical connection region through the first electrode layer, and an outer edge portion of the first electrode layer is located outside an outer edge portion of the electrical connection region.

An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.