Gigajot Technology, Inc.

First and second modulation gates disposed adjacent a silicon photoconversion structure generate, throughout the exposure interval, alternating first and second electrostatic fields that compel photocharge generated within the silicon photoconversion structure to the first and second storage diodes, respectively. Upon conclusion of the exposure interval, accumulated photocharge within the first and second storage diodes is transferred to first and second floating diffusion nodes, respectively, as part of a correlated-double-sampling readout with respect to each of the floating diffusion nodes.

An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

A dual operation correlated double sampling (CDS) readout circuit for implementation with a dual-conversion-gain (DCG) pixel is disclosed. The dual CDS readout circuit is capable of switching between a first readout mode that implements digital CDS and a second readout mode that implements analog CDS. In various implementations, the dual CDS readout circuit provides digital CDS operations when the DCG pixel outputs a high conversion gain (HCG) analog output signal. The dual CDS readout circuit may provide analog CDS operations when the DCG pixel outputs a low conversion gain (LCG) analog output signal.

A pixel of an image sensor may include an anti-blooming (AB) transistor with a gate formed in a shallow trench isolation (STI) of the pixel. The STI is positioned within the horizontal boundaries of the pixel structure. In certain instances, the STI isolates the drain region for a reset transistor of the pixel from a photodiode of the pixel and the AB transistor shares the drain region with the reset transistor. In such instances, the AB transistor may be turned on and provided a higher potential than the photodiode through its gate voltage to drain excess photoelectrons from the photodiode and prevent blooming due to oversaturation of the photodiode. In some instances, the gate of the AB transistor is formed in a separate STI and has its own drain formed next to the gate in the STI with the higher potential being provided through the gate or drain voltage.

First and second modulation gates disposed adjacent a silicon photoconversion structure generate, throughout the exposure interval, alternating first and second electrostatic fields that compel photocharge generated within the silicon photoconversion structure to the first and second storage diodes, respectively. Upon conclusion of the exposure interval, accumulated photocharge within the first and second storage diodes is transferred to first and second floating diffusion nodes, respectively, as part of a correlated-double-sampling readout with respect to each of the floating diffusion nodes.

An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

A sensing device includes a light source to emit light, a light sensor to detect reflection of the emitted light and distance determination circuitry responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector having a photocharge storage capacity in excess of one electron and an output circuit that generates an output signal responsive to light detection within the photodetector with sub-hundred nanosecond latency. The distance determination circuitry measures an elapsed time based on transition of the output signal in response to photonic detection within the photodetector and determines, based on the elapsed time, a distance between the sensing device and a surface that yielded the reflection of the emitted light.

Systems and methods are disclosed to enable fast readout from an image sensor to support pixel-wise conversion gain selection for high dynamic range imaging. In embodiments, an image sensor integrated circuit performs the pixel-wise gain selection with its readout circuitry, so that the image sensor outputs pixels with only the selected gain option. In this manner, the image sensor is able to achieve faster frame rates and lower power consumption. Depending on the embodiment, the conversion gain may be selected by the readout logic, an image signal processor, or an auto-exposure engine. The gain selection may be made based on a previous image captured by the camera or other pixels in the same image. The image signal processor may interpolate a high-gain and a low-gain portion of the image to obtain full resolution images in the two gain options, and merge the two to obtain the final image.

First and second readout circuits, each having a respective floating diffusion node, are coupled to a photodetection element within a pixel of an integrated-circuit image sensor. Following an exposure interval in which photocharge is accumulated within the photodetection element, a first portion of the accumulated photocharge is transferred from the photodetection element to the first floating diffusion node to enable generation of a first output signal within the first readout circuit, and a second portion of the accumulated photocharge is transferred from the photodetection element to the second floating diffusion node to enable generation of a second output signal within the second readout circuit. A digital pixel value is generated based on the first and second output signals.

Charge leakage/injection suppression circuitry within a capacitive programmable gain amplifier provides a low-impedance expulsion path for residual carriers within a feedback-path amplifier-mode switch and equalizes a voltage across a critical-leakage-path component of that amplifier-mode switch, reducing charge injection and leakage into an otherwise isolated amplifier input node to yield a low-noise amplifier output.