Glenfly Tech Co., Ltd.

The present disclosure relates to the computer technology and provides a method and a device for selecting a cache line to be replaced, and a storage medium. In the present disclosure, a blocking state binary tree is added to replace a replacement state binary tree, and a cache line to be replaced is selected based on the blocking state binary tree and a usage state binary tree, such that the earliest cache line, acting as the cache line to be replaced, can be accurately selected from the replaceable cache lines in a blocking cache.

The present disclosure relates to a method and apparatus for circuit board detection, a computer device, a storage medium, and a program product. The method includes: receiving a detection instruction; obtaining position information of board boundary corresponding to the at least one connector and preset cable boundary information corresponding to the at least one connector; detecting the at least one connector according to the position information corresponding to the board boundary of the at least one connector and the preset cable boundary information corresponding to the at least one connector to determine detection results of multiple detection items corresponding to the at least one connector, each detection item corresponding to a DFM abnormality type of connector; and determining a target detection result of the at least one connector according to the detection results of the multiple detection items corresponding to the at least one connector.

Programmable pixel blending method and apparatus, computer device, storage medium and computer program product are provided. The method includes: performing rasterization on a first triangle, a second triangle, and a third triangle via the raster unit to obtain triangle coverage information of each triangle; sending the triangle coverage information to the warp assembly unit and the warp reorder unit respectively; assembling, by the warp assembly unit, the first triangle and the second triangle into a first warp, and requesting a warp from a warp request interface based on information of the first warp; executing the first warp based on a warp information cache, a warp synchronization unit, the warp reorder unit, the pixel operation unit, the interpolation unit, and the execution unit; after the first warp is executed, continuing to assemble, by the warp assembly unit, the third triangle and completing a rendering of the third triangle.

The present disclosure relates to a method for detecting a region of interest in an image, a video encoding method, apparatuses, a computer device, a storage medium, and a computer program product. The method includes: obtaining a current to-be-detected image frame, determining a mapping block size parameter value from encoding parameters corresponding to the current to-be-detected image frame, dividing the current to-be-detected image frame to obtain multiple mapping blocks based on the mapping block size parameter value, performing a texture region detection on each mapping block to obtain a texture region of interest detection result. performing a motion region of interest detection on each mapping block to obtain a motion region of interest detection result, and determining a region of interest of the current to-be-detected image frame based on the texture region of interest detection result and the motion region of interest detection result.

The present disclosure relates to a multi-view image generation apparatus and method, and a graphics processing unit. Waves are constructed according to primitive information and vertex information of geometric primitives to generate a plurality of waves for parallel processing, and the waves are scheduled by a wave management unit for execution, which can improve execution efficiency. Since the primitive information of the geometric primitives is stored in a first cache unit, data sharing between waves can be implemented. During the parallel processing of the waves, vertex information in a second cache unit is updated in real time according to vertex address information outputted by the waves, so that a raster processing unit can read the latest vertex information from the second cache unit. Finally, through an image generation unit, a multi-view image is generated according to image colors obtained by executions of the waves and views corresponding to pixel points.

The present disclosure relates to a method for detecting a region of interest in an image, a video encoding method, apparatuses, a computer device, a storage medium, and a computer program product. The method includes: obtaining a current to-be-detected image frame, determining a mapping block size parameter value from encoding parameters corresponding to the current to-be-detected image frame, dividing the current to-be-detected image frame to obtain multiple mapping blocks based on the mapping block size parameter value, performing a texture region detection on each mapping block to obtain a texture region of interest detection result. performing a motion region of interest detection on each mapping block to obtain a motion region of interest detection result, and determining a region of interest of the current to-be-detected image frame based on the texture region of interest detection result and the motion region of interest detection result.

The present disclosure relates to a memory access processing method and apparatus, a computer device, a storage medium and a computer program. The method includes: acquiring a memory access request transmitted by a hardware module, the memory access request carrying a protection identifier, an access type, and an access area corresponding to the hardware module, the hardware module being pre-assigned with the corresponding protection identifier, and a memory area that the hardware module needs to access being pre-assigned to a memory region corresponding to an access permission; determining the memory region in which the access area is located; determining whether the protection identifier corresponding to the hardware module has the access permission for a corresponding access type to the memory region; and responding to the memory access request when the protection identifier corresponding to the hardware module has the access permission for the corresponding access type to the memory region.

Disclosed are parallel encoding and decoding method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: acquiring a synchronization node corresponding to a codec core, and transmitting a frame synchronization detection request to the synchronization node based on a frame to be encoded and decoded; acquiring a frame synchronization result corresponding to the frame synchronization detection request; and determining a encoding and decoding mode for the frame to be encoded and decoded based on the frame synchronization result, and encoding and decoding the frame to be encoded and decoded based on the encoding and decoding mode. By using the method, a plurality of codec cores can be employed to code and decode different frames in the same video in parallel, thereby improving the frame rate.

A pixel circuit includes a drive transistor, a data writing module, a storage module, and a light emitting control module; a first terminal of the storage module is configured to receive a first power supply voltage signal, and a second terminal of the storage module is configured to be connected to a control electrode of the drive transistor; a first terminal of the data writing module is configured to receive a data signal, and a second terminal of the data writing module is configured to be connected to the control electrode of the drive transistor; a substrate of the drive transistor is configured to receive a second voltage signal, a first electrode of the drive transistor is configured to receive the first power supply voltage signal, and a second electrode of the drive transistor is configured to be connected to at least partial light emitting control module.

A pixel circuit includes a drive transistor, a data writing module, a storage module, and a light emitting control module; a first terminal of the storage module is configured to receive a first power supply voltage signal, and a second terminal of the storage module is configured to be connected to a control electrode of the drive transistor; a first terminal of the data writing module is configured to receive a data signal, and a second terminal of the data writing module is configured to be connected to the control electrode of the drive transistor; a substrate of the drive transistor is configured to receive a second voltage signal, a first electrode of the drive transistor is configured to receive the first power supply voltage signal, and a second electrode of the drive transistor is configured to be connected to at least partial light emitting control module.