Company patents
GLOBAL UNICHIP CORPORATION
GLOBAL UNICHIP CORPORATION's patent strategy is heavily concentrated in semiconductor packaging, with Semiconductor Packaging & Encapsulation (24.8%), Multi-Chip & 3D Assemblies (23.8%), and Chip-to-Chip Interconnect (Bonding, Bumps) (20.0%) collectively representing nearly 70% of its portfolio. While these core areas saw significant growth in 2025 (e.g., Multi-Chip & 3D Assemblies grew by +83.3% YoY), the sharp decline in patent filings across most categories so far in 2026, including a -90.9% YoY drop in Semiconductor Packaging & Encapsulation and a -100.0% YoY drop in Electrical Measurement, suggests a potential shift in focus or a slowdown in new patent generation, though 2026 data is partial.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
105 US filings (since 2023) · 12 categories · 23 themes
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Techniques for measuring, monitoring, and compensating for temperature variations within semiconductor devices, integrated circuits, or photonic components to maintain performance, prevent degradation, and ensure reliability across operating conditions.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Techniques and circuits designed to identify, compensate for, or correct non-linearities, offsets, and other imperfections in signal processing paths, particularly within analog-to-digital, digital-to-analog, or digital-to-time converters.
Automated methods and tools for generating, optimizing, and verifying the physical layout and interconnections of electronic components, including integrated circuits, printed circuit boards, and system-level interface protection.
Focuses on the architectural and circuit-level innovations for Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to improve speed, accuracy, linearity, and power efficiency. Includes specific types like SAR and Delta-Sigma, and their constituent components.
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Methods and architectures for processing digital signals to enhance quality, remove noise, manage group delay, and facilitate symbol decision, often involving digital filters and equalization techniques.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
Systems and methods designed to improve the accuracy, reliability, or operational range of sensors and electronic components by measuring temperature and applying corrections or adjustments.
Temperature sensing systems integrated into wearable devices or medical apparatus for monitoring physiological conditions, such as inflammation detection, often utilizing differential temperature measurements.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Methods and devices for integrating temperature sensors directly into materials, structures, or challenging environments (e.g., hydrogen tanks, concrete, ocean) to measure internal or localized temperatures.
Patents
Showing 1-2 of 2
Memory System Performance & Reliability