Company patents
GlobalWafers Co., Ltd.
GlobalWafers Co. Ltd. shows a surprising shift in its patent strategy, with a significant decline in its core 'Semiconductor Manufacturing Process' category, which represents 32.5% of its portfolio, experiencing a -59.4% YoY drop so far in 2026. This is coupled with a near complete cessation of new patents in 'Transistor & Device Structure' (13.2% of portfolio), which saw a -100.0% YoY decline in 2026, while emerging areas like 'Semiconductor Diodes & Transistors' (4.6% of portfolio) saw 11 patents in 2025, indicating a potential pivot in focus despite a -54.5% YoY decline so far in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
348 US filings (since 2023) · 12 categories · 23 themes
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Methods for depositing thin films with controlled conformality, thickness, and material properties, including selective deposition on specific areas, often using atomic layer deposition (ALD), chemical vapor deposition (CVD), or epitaxial growth.
Specialized cleaning techniques and apparatus designed for removing microscopic contaminants, residues, or films from sensitive substrates, such as semiconductor wafers or flat panel displays, often involving chemical, mechanical, or plasma-based methods.
Synthesis and processing of silicon and silicon carbide materials in various forms (e.g., particles, nanowires, films) for applications beyond traditional semiconductors, such as battery components, refractories, or advanced electronics.
Methods and apparatus for cleaning polishing pads, dressers, chamber components, or finished substrates to remove residues, debris, or contaminants, often involving specialized nozzles, fluids, or mechanical actions.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.
Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Utilizing optical systems, cameras, and image processing algorithms for precise measurement of physical dimensions, alignment, defects, and features on semiconductor wafers or packages.
Integration of robotics, sensors, and control systems to automate the grinding, polishing, or deburring process, including workpiece handling, tool adjustment, and system maintenance for improved efficiency and precision.
Systems that employ imaging and image processing to automatically detect defects, verify states, or ensure quality control in manufactured goods, printed materials, or industrial processes.
Design and engineering of specialized components within deposition systems, such as heaters, targets, susceptors, and chamber walls, to achieve precise control over process parameters like temperature, material flux, and plasma characteristics.
Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Design and application of abrasive tools and deburring heads tailored for specific geometries, materials, or access constraints, including flexible, expandable, or multi-component designs for precision finishing.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Focuses on the chemical and physical properties of polishing slurries and the design of polishing pads, including their material composition, groove patterns, and thermal characteristics, to optimize chemical-mechanical planarization processes.
Techniques and devices for measuring, monitoring, and controlling the surface topography, film thickness, or other characteristics of a workpiece during or after grinding/polishing to achieve specific finish requirements.
Patents
Showing 1-10 of 526