Company patents
GRAPHCORE LIMITED
GRAPHCORE LIMITED's patent strategy reveals a surprising and significant decline across nearly all core computing categories, with "Operating Systems & Program Control" (43.0% of portfolio) seeing a -78.3% YoY drop in 2025 and "Computer Hardware Architecture" (37.8% of portfolio) experiencing a -50.0% YoY decline in both 2024 and 2025. This broad-based reduction in patenting, even in key areas like "Machine Learning & AI" which saw a -50.0% YoY decline in 2025, suggests a substantial shift away from aggressive IP protection in its foundational technologies, though "Physical Transmission & Modulation" shows an emerging focus with a +100.0% YoY growth in 2026 (so far).
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
135 US filings (since 2023) · 12 categories · 10 themes
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.
Design and configuration of adaptable frame structures, resource block groupings, and subcarrier spacings to optimize data transmission across diverse wireless environments and services, including considerations for fronthaul interfaces.
Enhancements to the physical and data link layers of network communication, focusing on hardware components, signal integrity, power efficiency, and efficient data transfer mechanisms for specific interfaces and buses.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Patents
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