HEFEI BOE DISPLAY TECHNOLOGY CO., LTD.

An array substrate, a display panel, a display device, and a method for manufacturing an array substrate are provided. The array substrate includes an array substrate; a plurality of data signal lines arranged on the base substrate; a plurality of fan-out lines arranged side-by-side on the base substrate and respectively lapped with the plurality of data signal lines through adapter holes; and a first test lead wire arranged on the base substrate, wherein the first test lead wire includes a first test pad, a first lead wire segment, and a second lead wire segment, the first lead wire segment is electrically connected to at least a part of the plurality of fan-out lines and arranged in a same layer as the fan-out lines, and the second lead wire segment is electrically connected to the first test pad and lapped with the first lead wire segment through an adapter hole.

A display panel has a plurality of sub-pixel regions arranged in an array of a plurality of rows and a plurality of columns, and a light-shielding region that separates the sub-pixel regions and surrounds all the sub-pixel regions as a whole. The display panel includes: a first substrate; a light-shielding pattern layer located on the first substrate, the light-shielding pattern layer being located in the light-shielding region and covering part of the light-shielding region; a second substrate disposed opposite to the first substrate; and a light-shielding structure layer located on the second substrate, the light-shielding structure layer covering at least a region of the light-shielding region that is not covered by the light-shielding pattern layer.

Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

A display panel has a plurality of sub-pixel regions arranged in an array of a plurality of rows and a plurality of columns, and a light-shielding region that separates the sub-pixel regions and surrounds all the sub-pixel regions as a whole. The display panel includes: a first substrate; a light-shielding pattern layer located on the first substrate, the light-shielding pattern layer being located in the light-shielding region and covering part of the light-shielding region; a second substrate disposed opposite to the first substrate; and a light-shielding structure layer located on the second substrate, the light-shielding structure layer covering at least a region of the light-shielding region that is not covered by the light-shielding pattern layer.

Provided is an array substrate, including: a substrate; a first insulating layer and a second insulating layer that are successively stacked; a first electrode disposed on a side, proximal to the substrate, of the first insulating layer; a second electrode disposed between the first insulating layer and the second insulating layer; and a lap electrode disposed on a side, distal from the substrate, of the second insulating layer. The array substrate includes a plurality of first vias and a plurality of second vias. The lap electrode is electrically connected to the first electrode and is electrically connected to the second electrode. An orthographic projection of the first electrode on the substrate is overlapped with an orthographic projection of the second electrode on the substrate, and covers a region between at least one of the first vias and at least one of the second vias.

The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L 1 , a length of a channel of each of at least a part of the multiple transistors for driving is a second length L 2 , and the first length L 1 is not equal to the second length L 2.

A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n−m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Provided is an array substrate which includes a base substrate; a plurality of common electrodes disposed on a side of the base substrate; a plurality of data lines disposed on a side of the base substrate, wherein with respect to each of the data lines, a distance between the data line and a first target common electrode is different from a distance between the data line and a second target common electrode; and a plurality of pixel electrodes arranged in an array and disposed on a side of the base substrate.

An edge-lit backlight module ( 7 ) includes a light guide plate ( 71 ), at least one polarizer ( 72 ) and at least one light source ( 73 ). The light guide plate ( 71 ) has side faces ( 71 a ). A polarizer ( 72 ) is disposed opposite to a side face ( 71 a ) of the light guide plate ( 71 ). A light source ( 73 ) is disposed on a side of a polarizer ( 72 ) away from the light guide plate ( 71 ). The at least one polarizer ( 72 ) is configured to convert light emitted from a light source ( 73 ) disposed on a side of the polarizer away from the light guide plate to the light guide plate ( 71 ) into linearly polarized light.