Hefei BOE Joint Technology Co., Ltd.

Pixel circuit, driving control method, display substrate and device are disclosed. The pixel circuit includes a driving circuit, a control circuit and a light-emitting module; the driving circuit generates driving current for driving the light-emitting module under control of control end of the driving circuit; the control circuit is connected to first scanning line, power supply voltage line and second end of the driving circuit, and controls connection between the power supply voltage line and the second end of the driving circuit under control of first scanning signal; second end of the light-emitting module is connected to a cathode voltage line. With the control circuit, branch current can be increased by increasing forward and reverse voltages, such that foreign bodies at dark spots can be burnt out and the dark spots can be changed into normal pixels, thereby improving product yield and displaying quality.

Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate; anodes and a mark pattern including at least one first mark pattern; a pixel defining layer having openings, wherein the orthographic projection of each opening on the base substrate at least partially overlaps with that of a corresponding anode, and the orthographic projection of the mark pattern on the base substrate is located within that of the pixel defining layer; at least one group of ink droplets including one or more ink droplets, and the orthographic projection of each ink droplet on the base substrate is located within that of the pixel defining layer; a functional layer including at least one sub-layer including a light-emitting layer, and the material of each group of ink droplets is the same as that of a sub-layer; and a cathode.

A scan circuit is provided. The scan circuit includes a random addressing circuit and a plurality of scan units. The random addressing circuit is configured to receive 2k number of control signals, and is configured to select at least one scan unit for outputting signals based on the 2k number of control signals. The plurality of scan units includes a plurality of scan unit groups. A respective scan unit group of the plurality of scan unit groups includes m number of scan units, and is configured to receive n number of clock signals. A respective scan unit of the m number of scan units in the respective scan unit group is configured to receive n′ number of clock signals, n′<n, n′ and n being positive integers. At least two scan units of the m number of scan units are configured to receive different combinations of clock signals.

Provided is a display device. A test circuit is provided in the display device, and the test circuit includes two first test lines extending in a first direction, the two ends of the first test line are disposed on the connection circuit board proximate to the first control assembly and proximate to the second control assembly, respectively, and the two first test lines are electrically connected to the second control assembly, so that the second control assembly transmits a test signal to one test line and receives the test signal from the other test line, determines the length of the connection circuit board based on the transmitting moment and the receiving moment of the test signal, and further determines the phase of the sampling clock based on the length of the connection circuit board.

Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel drive circuit, the pixel drive circuit is respectively connected with a scan signal line ( 41, 42 ) and a first power supply line ( 60 ); and in at least one sub-pixel, the scan signal line ( 41, 42 ) is provided with at least one fracture (K 1 , K 2 ), scan signal lines ( 41, 42 ) on both sides of the fracture (K 1 , K 2 ) are connected with each other through a signal connection electrode ( 91, 92 ), a length of the signal connection electrode ( 91, 92 ) is larger than a width of the first power supply line ( 60 ), and the length of the signal connection electrode ( 91, 92 ) is smaller than a width of the sub-pixel.

A display device includes: a display screen, a drive circuit, a first controller and a second controller. The display screen includes a first display region and a second display region. The drive circuit is configured to transmit a control signal to at least one of the first controller or the second controller. The first controller is configured to, responding to the control signal, perform a display control on the first display region. The second controller is configured to, responding to the control signal, perform a display control on the second display region. A display time difference between the first display region and the second display region is less than a threshold time period.

A shift register, includes a shift register unit and a first detection circuit electrically connected to the shift register unit. The shift register unit includes an input sub-circuit and an output sub-circuit. The input sub-circuit is configured to transmit a signal of an input signal terminal to a pull-up node under control of an input control terminal. The output sub-circuit is configured to receive a clock signal from a clock signal terminal, and provide an output signal to an output signal terminal based on the clock signal under control of a voltage at the pull-up node. The first detection circuit is electrically connected to the pull-up node and the clock signal terminal and is configured to obtain a voltage difference at the pull-up node within a first interval time, and perform compensation on a voltage of the clock signal based on the voltage difference at the pull-up node.

A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.

The display panel comprises a pixel driving circuit; the pixel driving circuit comprises a switching transistor; the display panel further comprises a base substrate, a first conductive layer, and a third conductive layer which are sequentially stacked; the first conductive layer is located on one side of the base substrate, and at least part of the first conductive layer is used for forming a gate of the switching transistor; the third conductive layer is located on the side of the first conductive layer facing away from the base substrate, the third conductive layer comprises a second signal line, and the second signal line is connected to the gate of the switching transistor by means of a via hole; the square resistance of the third conductive layer is less than the square resistance of the first conductive layer.

A display panel, a display apparatus and a method for manufacturing the display panel, which is related to the technical field of display. Including a back plate, wherein a planarization layer is arranged on the back plate; and the planarization layer is provided with a pixel defining layer setting area, and the pixel defining layer setting area includes a lyophilic area and a lyophobic area, wherein the lyophilic area and the lyophobic area are criss-cross arranged; the planarization layer is provided with a groove at a position where the lyophilic area is located; the groove is provided with a lyophilic pixel defining layer; and the lyophobic area is provided with a lyophobic pixel defining layer.