Hefei Reliance Memory Limited

The embodiments of the present application provide a method of making a chip with integrated memory and structure thereof. The method of making a chip with integrated memory comprising: forming a plurality of base memory arrays at a first process node in a memory wafer using a memory photomask set, wherein each of the base memory arrays is surrounded by a plurality of scribe lines; forming a plurality of control chips at a second process node in a control wafer using a control photomask set, wherein the first process node is more advanced than the second process node, and each of the control chips is configured to control an operation of a corresponding memory chip comprising at least two base memory arrays; bonding the memory wafer with the control wafer together to form a bonded wafer, wherein each control chip is bonded with the corresponding memory chip; and cutting the bonded wafer through a subset of, but not all of the scribe lines to form a plurality of chips with integrated memory, wherein each chip with integrated memory comprises a scribe line that was not cut.

The embodiments of the present application provide a memory device and a method for preforming a write operation in a memory device. The memory device comprising: a memory chip comprising a plurality of memory cells made at a first process node; and a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node; wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip.

An access transistor array for a memory device includes a plurality of active areas (AAs) formed on a substrate. Each AA includes a drain region and a source region arranged in a first direction (Y), with a polysilicon gate (POs) extending in a second direction (X) across the AA and separating the drain and source regions. Adjacent source regions in the second direction are connected, while adjacent drain regions in the second direction are separated by a shallow trench isolation (STI). This configuration reduces the poly-to-poly (PO-to-PO) spacing, decreasing the overall area required for each memory cell and enabling higher memory densities.

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W 1. The top electrode has a top surface that has a second width W 2 between two edges of the top surface. The memory cell has a first height H 1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W 3, a second height H 2 at a location between two adjacent memory cells, and a third height H 3 extending between the top surface of the top contact wire and the insulating layer, where W 1> W 3> W 2 and H 2> H 1> H 3.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W 1 . The top electrode has a top surface that has a second width W 2 between two edges of the top surface. The memory cell has a first height H 1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W 3 , a second height H 2 at a location between two adjacent memory cells, and a third height H 3 extending between the top surface of the top contact wire and the insulating layer, where W 1 >W 3 >W 2 and H 2 >H 1 >H 3.

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

A display driver integrated circuit includes an input port configured to receive a display sensing signal for a display panel; a resistive random access memory coupled to the input port and configured to store a sensing value indicative of the display sensing signal; a display compensation logic coupled to the resistive random access memory to receive the sensing value and configured to determine, based on the sensing value, a compensation value to enable the display panel to modify a display control signal; and an output port coupled to the display compensation logic to transmit a display compensation voltage signal to the display panel. The display compensation voltage signal is generated based on the compensation value.