UnfoldIP

Company patents

iCometrue Company Ltd.

iCometrue Company Ltd. shows a strong focus on core semiconductor technologies, with Pulse / Digital Logic Circuits (65.1% of portfolio) and Multi-Chip & 3D Assemblies (61.4% of portfolio) being dominant. While most semiconductor categories saw significant growth in 2025, there's a surprising shift in 2026 with substantial year-to-date declines across many of these, such as Chip-to-Chip Interconnect (Bonding, Bumps) dropping by 96.2% and Semiconductor Packaging & Encapsulation by 88.5% so far, suggesting a potential re-evaluation of priorities, even as Electronic Design Automation (CAD/EDA) emerges as a rapidly growing focus with a 150.0% YoY increase in 2026.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

83 US filings (since 2023) · 12 categories · 8 themes

Heterogeneous Chiplet Integration

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Multi-Chip & 3D AssembliesMemory Devices (Structural)
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63since 2023
+84.6%YoY
3D Die Stacking & Vertical Interconnectsfiltered

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Semiconductor Packaging & EncapsulationChip-to-Chip Interconnect (Bonding, Bumps)Multi-Chip & 3D AssembliesMemory Devices (Structural)Semiconductor Diodes & Transistors
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29since 2023
+133.3%YoY
Fan-Out & Embedded Die Packaging

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Multi-Chip & 3D AssembliesSemiconductor Packaging & EncapsulationChip-to-Chip Interconnect (Bonding, Bumps)
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19since 2023
+40.0%YoY
Advanced Package Interconnects

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Semiconductor Packaging & Encapsulation
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18since 2023
0.0%YoY
Power Switching & Drivers

Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.

Pulse / Digital Logic Circuits
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10since 2023
-66.7%YoY
Resistive & Phase Change Memory

Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.

Memory Devices (Structural)Inorganic Devices (Thermoelectric, Piezo)
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5since 2023
+200.0%YoY
Package Thermal Management

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Multi-Chip & 3D AssembliesSemiconductor Packaging & EncapsulationSemiconductor Manufacturing Process
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1since 2023
new
Advanced Memory Cell Structures

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Memory Devices (Structural)
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1since 2023
new

Patents

Showing 1-10 of 43

3D Die Stacking & Vertical Interconnects
Page 1 of 5
US 20260114256 A1APPLICATION
H01L23/528

VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS

Filed:2024-11-18Pub:2026-04-23
Applicant:iCometrue Company Ltd.

A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

US 20260004035 A1APPLICATION
G06F30/34

LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS

Filed:2024-12-15Pub:2026-01-01
Applicant:iCometrue Company Ltd.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

US 20250316607 A1APPLICATION
H01L23/538

LOGIC DRIVE BASED ON MULTICHIP PACKAGE COMPRISING STANDARD COMMODITY FPGA IC CHIP WITH COOPERATING OR SUPPORTING CIRCUITS

Filed:2025-03-30Pub:2025-10-09
Applicant:iCometrue Company Ltd.

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.

US 20250273579 A1APPLICATION
H01L23/538

LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP

Filed:2025-05-11Pub:2025-08-28
Applicant:iCometrue Company Ltd.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

US 20250253290 A1APPLICATION
H01L25/065

LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP

Filed:2025-04-23Pub:2025-08-07
Applicant:iCometrue Company Ltd.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

US 12354966 B2GRANTED
H01L23/52

Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

Filed:2023-08-01Pub:2025-07-08
Applicant:iCometrue Company Ltd.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

US 12327816 B2GRANTED
H01L25/065

Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

Filed:2023-03-15Pub:2025-06-10
Applicant:iCometrue Company Ltd.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

US 12327790 B2GRANTED
H01L23/528

Vertical interconnect elevator based on through silicon vias

Filed:2024-01-07Pub:2025-06-10
Applicant:iCometrue Company Ltd.

A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

US 20250149505 A1APPLICATION
H01L25/065

LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP

Filed:2025-01-12Pub:2025-05-08
Applicant:iCometrue Company Ltd.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

US 20250149504 A1APPLICATION
H01L25/065

LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP

Filed:2025-01-12Pub:2025-05-08
Applicant:iCometrue Company Ltd.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

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