Imagination Technologies Limited

Methods and systems for identifying quantisation parameters for a Deep Neural Network (DNN). The method includes determining an output of a model of the DNN in response to training data, the model of the DNN comprising one or more quantisation blocks configured to transform a set of values input to a layer of the DNN prior to processing the set of values in accordance with the layer, the transformation of the set of values simulating quantisation of the set of values to a fixed point number format defined by one or more quantisation parameters; determining a cost metric of the DNN based on the determined output and a size of the DNN based on the quantisation parameters; back-propagating a derivative of the cost metric to one or more of the quantisation parameters to generate a gradient of the cost metric for each of the one or more quantisation parameters; and adjusting one or more of the quantisation parameters based on the gradients.

A tiling unit assigning primitives to tiles in a graphics processing system which has rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.

A processor has a processing module a ray engine. The ray engine comprises a ray store and ray-tracing circuitry. The ray-engine comprises control logic which: receives a plurality of batches of ray descriptors supplied from the processing module, each batch comprising respective ray descriptors of a plurality of modelled rays; and allocates ray descriptors to address space of the ray store in blocks of ray descriptors, each block being a subset of the ray descriptors in the batch, and stores each block in the allocated address space. For each batch of ray descriptors, the ray-tracing circuitry processes each of the rays of the batch based on the respective ray descriptors stored in the ray store. For each block, the control logic deallocates the memory allocated to the block in response to the processing of all the rays in the block being finished by the ray-tracing engine.

Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.

Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data. Ray tracing systems and computer-implemented methods for performing intersection testing in the ray tracing system determine whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.

A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Frames are rendered in a graphics processing unit representing views of a scene in a rendering space subdivided into a plurality of tiles. Tiles of a group of frames are rendered in an interspersed order such that the frame from which a tile is rendered switches back and forth between the frames of the group of frames, wherein the view represented by each frame in the group of frames is a view of the scene at a different time instance, wherein at least one transformation indicates tiles which are likely to be similar in different frames of the group of frames, wherein the interspersed order is based on the at least one transformation such that said rendering comprises rendering similar tiles from the frames of the group of frames sequentially.

A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core and assigns a second subset of the image rendering tasks to a second core. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.

A method and system for processing a set of k floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (m i ) and an exponent (e i ). The method comprises receiving the set of k floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (m i ) with a bit-length of b bits. The method further comprises creating a set of k numbers (y i ) based on the mantissas of the k floating-point numbers, the numbers having a bit-length of n bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length b of the mantissa (m i ). The method includes identifying a maximum exponent (e max ) among the exponents e i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent (e max ) and processing the set of k numbers concurrently.

Methods and systems of generating gradients of a loss metric for a neural network (NN) with respect to weights of a convolution layer of the NN, the convolution layer of the NN configured to receive an input tensor of input values and a weight tensor of weights, and generate an output tensor of output values. The methods comprise performing, using hardware logic, a group convolution between a first y-dimensional tensor and a second z-dimensional tensor wherein z=y+1, the first y-dimensional tensor being formed of a set of values from the input tensor, and the second z-dimensional tensor being formed of a set of values from an output gradient tensor comprising gradients of the loss metric for the NN with respect to the output values; wherein the first y-dimensional tensor, the second z-dimensional tensor and the group convolutions are configured to generate an output of a convolution operation between each channel of the set of values of the input tensor and each channel of the set of values of the output gradient tensor.