Infineon Technologies LLC

Systems, methods, and devices provide error correction in such nonvolatile memories. Methods include identifying a read operation associated with a nonvolatile memory array, performing a plurality of sensing operations on the nonvolatile memory array, the plurality of sensing operations comprising a plurality of comparisons between sensed values and reference values, and generating a plurality of data outputs based on the plurality of sensing operations. Methods further include generating a plurality of results based on the plurality of data outputs, wherein each of the plurality of results identifies a number of errors associated with at least one of the plurality of data outputs, and selecting a data output of the plurality of data outputs based, at least in part, on the identified number of errors.

Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.

According to some embodiments, a device includes a reference supply pad, a negative supply pad, a resistor connected to the negative supply pad, and a first transistor connected to the reference supply pad and the negative supply pad and having a first gate electrode connected to the resistor, wherein responsive to an electrostatic voltage being applied to one of the reference supply pad or the negative supply pad, the first transistor is operable to shunt current to the negative supply pad.

Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.

A semiconductor device and methods of fabricating the same are disclosed. Generally, the method includes forming a tunnel-dielectric for a memory transistor over a surface of a substrate, forming a nitride charge-trapping layer over the tunnel-dielectric, and forming a gate-dielectric for a field-effect transistor over the surface of the substrate. Forming the gate-dielectric can include performing a number of oxidation processes to form a thick gate-oxide while concurrently forming a blocking-dielectric including an oxide layer over the charge-trapping layer of the memory transistor. In one embodiment, performing the oxidation processes includes performing an in-situ-steam-generation process to form the thick gate-oxide and the oxide layer of the blocking-dielectric, followed by a thermal oxidation process to increase a thickness of the thick gate-oxide and the oxide layer without altering a substantially uniform stoichiometric concentration of nitrogen across a thickness of the charge-trapping layer from the tunnel-dielectric to the blocking-dielectric.

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include a non-volatile memory (NVM) transistor form over a substrate having a buried lower source/drain (S/D) junction, an upper S/D junction, a vertical channel having a cylindrical shape disposed between the upper and lower S/D junctions, a cylindrical memory film stack surrounding the vertical channel, and a gate layer disposed around the memory film stack. The semiconductor devices may also include word lines surrounding the vertical channels, bit lines and source lines connecting multiple NVM transistors. Other embodiments are also described.

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor device may include a first region including at least one non-volatile memory (NVM) transistor having a lower source/drain (S/D) junction and an upper S/D junction, a vertical channel disposed between the upper and lower S/D junctions and surrounded by a cylindrical memory film stack, and a gate layer disposed around the memory film stack, the device also include a second region including at least one logic transistor each having a gate dielectric layer overlying a horizontal channel, a gate layer, and a height-enhancement layer. Other embodiments are also described.

A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

An integrated circuit includes an array of flash memory and flash translation layer (FTL) logic coupled to the array and to be coupled to a host device. The FTL logic is configured to receive, from the host device, a write command comprising a first logical address, user data, and an access token and translate the first logical address to a first physical address of the array. In an embodiment, the first physical address has already been programmed. The FTL logic is further to verify the access token as being associated with the first logical address, cause the user data to be programmed to a second physical address of the array, and update at least one logical-to-physical (L2P) mapping table with the second physical address as being mapped to the first logical address.

A method can include determining the CS signal has transitioned from inactive to active and receiving at least target address information at a bus interface of the IC device. In response to target address information, retrieving data stored at a corresponding storage location of the IC device. By operation of authentication circuits, generating an authentication value using at least one cryptographic function that includes at least the authentication parameters and the retrieved data. The authentication value can be transmitted with retrieved data from the IC device. Corresponding devices and systems are also disclosed.