Company patents
InnoGrit Technologies Co., Ltd.
InnoGrit Technologies Co., Ltd. shows a surprising shift in its patent strategy, moving away from its core strengths in Memory & Storage (Static) and Computer Hardware Architecture, which have seen significant declines of -40.0% and -45.5% respectively in 2025. While Input/Output & User Interfaces remains its largest category at 31.9% of its portfolio, its patenting in this area has also sharply declined by -43.8% in 2025, suggesting a broad retrenchment in patent filings across its primary technology domains, with only Coding & Decoding showing a modest increase of +33.3% so far in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
113 US filings (since 2023) · 9 categories · 14 themes
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.
Development of encoding and decoding algorithms and apparatuses for robust data transmission and storage, focusing on techniques like LDPC, polar codes, and iterative decoding methods to minimize bit errors and improve communication reliability.
Methods and systems for efficiently reducing the size of digital data, often employing adaptive techniques, neural networks, or temporal modeling, to achieve high compression ratios while preserving data quality. Includes entropy coding.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Techniques for protecting data at rest or in backup, ensuring its integrity, confidentiality, and verifiable origin, often involving encryption, unique identifiers, or secure repositories.
Techniques and circuits designed to identify, compensate for, or correct non-linearities, offsets, and other imperfections in signal processing paths, particularly within analog-to-digital, digital-to-analog, or digital-to-time converters.
Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.
Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.
Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.
Patents
Showing 1-10 of 12
Advanced Memory Cell Structures