INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.

A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based transition layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by applying a first V/III ratio in a first range. The second III-V nitride-based layer is disposed over the first III-V nitride-based layer by applying a second V/III ratio in a second range, in which the first range and the second range are mutually exclusive. The nitride-based transition layer is disposed between the first III-V nitride-based layer and the second III-V nitride-based layer to connect the first III-V nitride-based layer with the second III-V nitride-based layer, in which the nitride-based transition layer is formed by applying a third V/III ratio in a third range between the first range and second range. The nitride-based transistor is disposed over the second III-V nitride-based layer.

A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based semiconductor layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by applying a first V/III ratio. The first III-V nitride-based layer has a first concentration of a group III element. The second III-V nitride-based layer is disposed on the first III-V nitride-based layer by applying a second V/III ratio less than the first V/III ratio. The second III-V nitride-based layer has a second concentration of the group III element less than the first concentration. The second concentration decreases along a direction away from the first III-V nitride-based layer, such that a first variance in the first concentration is less than a second variance in the second concentration. The nitride-based semiconductor layer is disposed over the second III-V nitride-based layer.

A nitride-based semiconductor device includes III-V nitride-based buffer layer, a first III-V nitride-based semiconductor layer, and second III-V nitride-based semiconductor layer. The III-V nitride-based buffer layer is disposed over a substrate to form a first interface with the substrate. The III-V nitride-based buffer layer has a plurality of first dislocation lines extending from the first interface to a top surface of the III-V nitride-based buffer layer. The first III-V nitride-based semiconductor layer is disposed over the III-V nitride-based buffer layer to form a second interface with the top surface of the III-V nitride-based buffer layer. The first III-V nitride-based semiconductor layer has a plurality of second dislocation lines. Each of the second dislocation lines connects two of the first dislocation lines. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer.

A semiconductor apparatus and a method of manufacturing the same are provided. A semiconductor apparatus includes a first nitride semiconductor layer, a second nitride semiconductor layer, an electrode, a dielectric structure, a field plate, a plurality of height compensators, and a plurality of vias. The second nitride semiconductor layer is on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The electrode contacts the second nitride semiconductor layer. The dielectric structure is disposed on the second nitride semiconductor layer and covers the electrode. The field plate is in the dielectric structure. The height compensators are in the dielectric structure and are disposed on the electrode and the field plate, respectively. The vias extend into the dielectric structure and contact top surfaces of the height compensators, respectively.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode, a first electrode, a first via and a second via. The substrate has a first surface and a second surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap exceeding that of the first nitride semiconductor layer. The gate electrode and the first electrode are disposed on the second nitride semiconductor layer. The first via extends from the second surface and is electrically connected to the first electrode. The second via extends from the second surface. The depth of the first via is different from the depth of the second via.

A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

An integrated semiconductor device includes a substrate, semiconductor circuit layers, an insulating material, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The insulating material is disposed on the semiconductor circuit layers, and the interconnection layer is embedded in the insulating material and electrically connected to the semiconductor circuit layers. The isolating portions provide electrical isolation between adjacent device portions. The interconnection layer has circuits embedded in the insulating material on the device portions. The insulating material has isolating structures raised from top surfaces of the circuits on the device portion, and some of the semiconductor circuit layers form at least one heterojunction.

An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers. The interconnection layer has a plurality of first circuits located above the device portions.

An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers. The interconnection layer has a plurality of first circuits located above the device portions.

A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.