INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.

Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.

Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.

Specialized circuits and devices designed to protect electrical and electronic systems from transient overvoltages caused by electrostatic discharge (ESD) or power surges, often involving suppressor diodes, gas discharge tubes (GDTs), or voltage clamping mechanisms.

Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Circuit breaker designs that combine mechanical switches with power semiconductors or solely use solid-state components to achieve faster fault interruption, current limiting, and arc suppression in AC or DC power systems.

Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.

Techniques and circuits for accurately identifying various electrical faults, such as ground faults, overcurrent, short circuits, switch malfunctions, or electrostatic discharge (ESD) events, often utilizing sensors, signal processing, and diagnostic algorithms.