Intel IP Corporation

A base station may generate first configuration information to configure a first user equipment (“UE”) to operate using a first bandwidth within a wideband carrier of a cell, generate second configuration information to configure a second UE to operate using a second bandwidth within the wideband carrier of the cell, and cause transmission of the first and second configuration information to the first and second UEs, respectively. The base station may configure the first and second UEs based upon capabilities received from each UE, respectively.

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

The first circuitry may be operable to establish a first UE Receive (Rx) beam as being for reception of data from a first eNB. The second circuitry may be operable to process a transmission including Downlink Control Information (DCI), wherein the DCI carries an eNB cell-switching indicator. The first circuitry may also be operable to establish a second UE Rx beam as being for reception of data from a second eNB based on the eNB cell-switching indicator.

In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

In one embodiment, an apparatus includes memory storing instructions and processing circuitry coupled to the memory. The processing circuitry is to implement the instructions to select a resource block group (RBG) size configuration from a set of RBG size configurations based on a bandwidth part (BWP) size. Each RBG size configuration is to indicate RBG sizes associated with respective ranges of BWP sizes, and the RBG sizes are to indicate a number of frequency-domain physical resource blocks (PRBs) for physical downlink shared channel (PDSCH) or physical uplink shared channel (PUSCH) transmissions. The processing circuitry is further to implement the instructions to allocate PRBs for communication between the gNB device and a user equipment (UE) device via the PDSCH or PUSCH transmissions based on the selected RBG size, and to encode downlink control information (DCI) that indicates the allocated PRBs for transmission to the UE device.

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

For example, an apparatus may include a video encoder configured to encode video data into a parallel plurality of encoded video streams, the parallel plurality of encoded video streams including the video data encoded according to a respective plurality of different video bitrates; a selector configured to select, based on one or more parameters corresponding to a condition of a wireless communication link, a selected encoded video stream from the parallel plurality of encoded video streams; and a radio to transmit the selected encoded video stream over the wireless communication link.

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.

A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor w i,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor w i,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.