Kandou Labs, S.A.

Methods and systems are described herein for exchanging retimer training status and state machine (RTSSM) status information between a plurality of circuit dies of a multi-chip module utilizing a ring bus configured to carry a multi-bit lane status signal using a plurality of time slots, the ring bus interconnecting the plurality of circuit dies into a ring of circuit dies, wherein each circuit die outputs stored aggregate RTSSM status information onto the ring bus to the next circuit die in the ring and stores the aggregate RTSSM status information from the preceding circuit die in the ring until each circuit die accrues the complete multi-die RTSSM status information for all of the circuit dies. Based on the complete multi-die RTSSM status information, each circuit die may synchronously execute state changes in the upstream and/or downstream RTSSMs on the circuit die.

Methods and systems are described for calculating lane-to-lane skew parameters from detected alignment symbols during a skew measurement mode of operation, detecting a command to switch from skew measurement mode to a transparent mode of operation, wherein each of the plurality of encoded data streams are routed to respective low-latency CDC FIFOs configured to store the encoded data streams using respective write clocks and to output encoded data streams based on corresponding read clocks, each read clock synchronized to a corresponding write clock, and adjusting a timing of a first encoded data stream relative to a second encoded data stream based on the set of lane-to-lane skew parameters generated in the PCS to reduce lane-to-lane skew.

Methods and systems are described for performing multi-lane alignment and rate adaptation between tiles ( 1304, 1302 ) in a multi¬file package ( 1300 ), specifically exchanging alignment information (algn_found, rpcs_algn_ctl) across clock domains for different tiles ( 1304, 1302 ) based on a write tile clock (wr_tile_clk) generated from a local system clock (tx_clk) in a leader tile ( 1302 ), the write tile clock (wr_tile_clock) having a period equal to a common reference clock (refclk), the write tile clock (wr_tile_clock) corresponding to a pulse having a location within the period of the common reference clock (refclk) as determined by an active cycle of a counter.

Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.

Techniques for updating message definitions used by a PCIe component such as a retimer are described. The message definitions are provided within a firmware image that is checked for validity and authenticity during a firmware update process. This enables in-field updating of the message definitions in a secure manner, making it possible to securely expand or adjust the functionality offered by the component deployed in the field. In the case where the component is a retimer, the functionality can include delay buffer and/or lane routing settings that result in a reduced lane-to-lane skew. Techniques for in-band transmission of a data package such as a firmware update are also described.

Methods and systems are described for receiving, at an upstream-facing pseudo-port of a retimer, a telemetry request command via one or more control skip-ordered sets (C-SKPs), the telemetry request command including one of a plurality of telemetry IDs respectively identifying types of telemetry data, the types of telemetry data selected from the group consisting of: retimer training and status state machine (RTSSM) state information and temperature data, retrieving telemetry data from the retimer associated with the telemetry ID in the telemetry request command, receiving, at a downstream-facing pseudo-port of the retimer, C-SKPs, and responsively generating modified C-SKPs by rewriting fields of the received C-SKPs with the retrieved telemetry data, and transmitting the modified C-SKPs via the upstream-facing pseudo-port.

Methods and systems for receiving a differential input voltage signal at an input of a variable gain amplifier, and responsively generating an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal, enabling a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal, and reducing a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal.

A feedthrough switch that prevents, in a blocking mode, voltage signals from being transmitted via a feedthrough path, comprising a cascode circuit comprising two PMOS devices coupled in series. One of the PMOS devices is coupled to receive an input voltage signal at its source and the other coupled to a center node. A gate of each PMOS is biased using a biasing circuit including a voltage follower that provides a biasing voltage that tracks the input voltage signal up to a supply voltage of the voltage follower. The biasing voltage keeps both PMOS devices in a non-conductive state while the voltage signal is below the supply voltage. An overstress prevention voltage supply is coupled to the center node and maintains the center node at a fixed voltage to ensure that both PMOS devices remain within their respective rated voltages across the full range of the voltage signal.

Methods and systems are described for a retimer module comprising a first cable connector and a second cable connector, a peripheral component interconnect express (PCIe) retimer die comprising one or more upstream PHYs coupled to the first cable connector and one or more downstream PHYs coupled to the second cable connector, the PCIe retimer die further comprising an I 2 C input coupled between designated I 2 C pins of the first and second cable connectors, a voltage regulator module (VRM) configured to receive a supply voltage via a pin of the first cable connector, to responsively generate a plurality of regulated supply voltages, and to provide the plurality of regulated supply voltages to the retimer die, and a casing containing the retimer die and the voltage regulator module, the casing comprising a fastener for mounting to a chassis.

Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.